1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-orion5x/rd88f6183-ap-ge-setup.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Marvell Orion-1-90 AP GE Reference Design Setup
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
8*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/gpio.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
17*4882a593Smuzhiyun #include <linux/mv643xx_eth.h>
18*4882a593Smuzhiyun #include <linux/spi/spi.h>
19*4882a593Smuzhiyun #include <linux/spi/flash.h>
20*4882a593Smuzhiyun #include <linux/ethtool.h>
21*4882a593Smuzhiyun #include <linux/platform_data/dsa.h>
22*4882a593Smuzhiyun #include <asm/mach-types.h>
23*4882a593Smuzhiyun #include <asm/mach/arch.h>
24*4882a593Smuzhiyun #include <asm/mach/pci.h>
25*4882a593Smuzhiyun #include "common.h"
26*4882a593Smuzhiyun #include "orion5x.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = {
29*4882a593Smuzhiyun .phy_addr = -1,
30*4882a593Smuzhiyun .speed = SPEED_1000,
31*4882a593Smuzhiyun .duplex = DUPLEX_FULL,
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static struct dsa_chip_data rd88f6183ap_ge_switch_chip_data = {
35*4882a593Smuzhiyun .port_names[0] = "lan1",
36*4882a593Smuzhiyun .port_names[1] = "lan2",
37*4882a593Smuzhiyun .port_names[2] = "lan3",
38*4882a593Smuzhiyun .port_names[3] = "lan4",
39*4882a593Smuzhiyun .port_names[4] = "wan",
40*4882a593Smuzhiyun .port_names[5] = "cpu",
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static struct mtd_partition rd88f6183ap_ge_partitions[] = {
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun .name = "kernel",
46*4882a593Smuzhiyun .offset = 0x00000000,
47*4882a593Smuzhiyun .size = 0x00200000,
48*4882a593Smuzhiyun }, {
49*4882a593Smuzhiyun .name = "rootfs",
50*4882a593Smuzhiyun .offset = 0x00200000,
51*4882a593Smuzhiyun .size = 0x00500000,
52*4882a593Smuzhiyun }, {
53*4882a593Smuzhiyun .name = "nvram",
54*4882a593Smuzhiyun .offset = 0x00700000,
55*4882a593Smuzhiyun .size = 0x00080000,
56*4882a593Smuzhiyun },
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static struct flash_platform_data rd88f6183ap_ge_spi_slave_data = {
60*4882a593Smuzhiyun .type = "m25p64",
61*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(rd88f6183ap_ge_partitions),
62*4882a593Smuzhiyun .parts = rd88f6183ap_ge_partitions,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static struct spi_board_info __initdata rd88f6183ap_ge_spi_slave_info[] = {
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun .modalias = "m25p80",
68*4882a593Smuzhiyun .platform_data = &rd88f6183ap_ge_spi_slave_data,
69*4882a593Smuzhiyun .max_speed_hz = 20000000,
70*4882a593Smuzhiyun .bus_num = 0,
71*4882a593Smuzhiyun .chip_select = 0,
72*4882a593Smuzhiyun },
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
rd88f6183ap_ge_init(void)75*4882a593Smuzhiyun static void __init rd88f6183ap_ge_init(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * Setup basic Orion functions. Need to be called early.
79*4882a593Smuzhiyun */
80*4882a593Smuzhiyun orion5x_init();
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * Configure peripherals.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun orion5x_ehci0_init();
86*4882a593Smuzhiyun orion5x_eth_init(&rd88f6183ap_ge_eth_data);
87*4882a593Smuzhiyun orion5x_eth_switch_init(&rd88f6183ap_ge_switch_chip_data);
88*4882a593Smuzhiyun spi_register_board_info(rd88f6183ap_ge_spi_slave_info,
89*4882a593Smuzhiyun ARRAY_SIZE(rd88f6183ap_ge_spi_slave_info));
90*4882a593Smuzhiyun orion5x_spi_init();
91*4882a593Smuzhiyun orion5x_uart0_init();
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun static struct hw_pci rd88f6183ap_ge_pci __initdata = {
95*4882a593Smuzhiyun .nr_controllers = 2,
96*4882a593Smuzhiyun .setup = orion5x_pci_sys_setup,
97*4882a593Smuzhiyun .scan = orion5x_pci_sys_scan_bus,
98*4882a593Smuzhiyun .map_irq = orion5x_pci_map_irq,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
rd88f6183ap_ge_pci_init(void)101*4882a593Smuzhiyun static int __init rd88f6183ap_ge_pci_init(void)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun if (machine_is_rd88f6183ap_ge()) {
104*4882a593Smuzhiyun orion5x_pci_disable();
105*4882a593Smuzhiyun pci_common_init(&rd88f6183ap_ge_pci);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun subsys_initcall(rd88f6183ap_ge_pci_init);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
113*4882a593Smuzhiyun /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
114*4882a593Smuzhiyun .atag_offset = 0x100,
115*4882a593Smuzhiyun .nr_irqs = ORION5X_NR_IRQS,
116*4882a593Smuzhiyun .init_machine = rd88f6183ap_ge_init,
117*4882a593Smuzhiyun .map_io = orion5x_map_io,
118*4882a593Smuzhiyun .init_early = orion5x_init_early,
119*4882a593Smuzhiyun .init_irq = orion5x_init_irq,
120*4882a593Smuzhiyun .init_time = orion5x_timer_init,
121*4882a593Smuzhiyun .fixup = tag_fixup_mem32,
122*4882a593Smuzhiyun .restart = orion5x_restart,
123*4882a593Smuzhiyun MACHINE_END
124