xref: /OK3568_Linux_fs/kernel/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Marvell Orion-VoIP GE Reference Design Setup
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun  * License version 2.  This program is licensed "as is" without any
8*4882a593Smuzhiyun  * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun #include <linux/gpio.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/irq.h>
16*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
17*4882a593Smuzhiyun #include <linux/mv643xx_eth.h>
18*4882a593Smuzhiyun #include <linux/ethtool.h>
19*4882a593Smuzhiyun #include <linux/i2c.h>
20*4882a593Smuzhiyun #include <linux/platform_data/dsa.h>
21*4882a593Smuzhiyun #include <asm/mach-types.h>
22*4882a593Smuzhiyun #include <asm/mach/arch.h>
23*4882a593Smuzhiyun #include <asm/mach/pci.h>
24*4882a593Smuzhiyun #include "common.h"
25*4882a593Smuzhiyun #include "mpp.h"
26*4882a593Smuzhiyun #include "orion5x.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /*****************************************************************************
29*4882a593Smuzhiyun  * RD-88F5181L GE Info
30*4882a593Smuzhiyun  ****************************************************************************/
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun  * 16M NOR flash Device bus boot chip select
33*4882a593Smuzhiyun  */
34*4882a593Smuzhiyun #define RD88F5181L_GE_NOR_BOOT_BASE		0xff000000
35*4882a593Smuzhiyun #define RD88F5181L_GE_NOR_BOOT_SIZE		SZ_16M
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /*****************************************************************************
39*4882a593Smuzhiyun  * 16M NOR Flash on Device bus Boot chip select
40*4882a593Smuzhiyun  ****************************************************************************/
41*4882a593Smuzhiyun static struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = {
42*4882a593Smuzhiyun 	.width		= 1,
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun static struct resource rd88f5181l_ge_nor_boot_flash_resource = {
46*4882a593Smuzhiyun 	.flags		= IORESOURCE_MEM,
47*4882a593Smuzhiyun 	.start		= RD88F5181L_GE_NOR_BOOT_BASE,
48*4882a593Smuzhiyun 	.end		= RD88F5181L_GE_NOR_BOOT_BASE +
49*4882a593Smuzhiyun 			  RD88F5181L_GE_NOR_BOOT_SIZE - 1,
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun static struct platform_device rd88f5181l_ge_nor_boot_flash = {
53*4882a593Smuzhiyun 	.name			= "physmap-flash",
54*4882a593Smuzhiyun 	.id			= 0,
55*4882a593Smuzhiyun 	.dev		= {
56*4882a593Smuzhiyun 		.platform_data	= &rd88f5181l_ge_nor_boot_flash_data,
57*4882a593Smuzhiyun 	},
58*4882a593Smuzhiyun 	.num_resources		= 1,
59*4882a593Smuzhiyun 	.resource		= &rd88f5181l_ge_nor_boot_flash_resource,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /*****************************************************************************
64*4882a593Smuzhiyun  * General Setup
65*4882a593Smuzhiyun  ****************************************************************************/
66*4882a593Smuzhiyun static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
67*4882a593Smuzhiyun 	MPP0_GPIO,		/* LED1 */
68*4882a593Smuzhiyun 	MPP1_GPIO,		/* LED5 */
69*4882a593Smuzhiyun 	MPP2_GPIO,		/* LED4 */
70*4882a593Smuzhiyun 	MPP3_GPIO,		/* LED3 */
71*4882a593Smuzhiyun 	MPP4_GPIO,		/* PCI_intA */
72*4882a593Smuzhiyun 	MPP5_GPIO,		/* RTC interrupt */
73*4882a593Smuzhiyun 	MPP6_PCI_CLK,		/* CPU PCI refclk */
74*4882a593Smuzhiyun 	MPP7_PCI_CLK,		/* PCI/PCIe refclk */
75*4882a593Smuzhiyun 	MPP8_GPIO,		/* 88e6131 interrupt */
76*4882a593Smuzhiyun 	MPP9_GPIO,		/* GE_RXERR */
77*4882a593Smuzhiyun 	MPP10_GPIO,		/* PCI_intB */
78*4882a593Smuzhiyun 	MPP11_GPIO,		/* LED2 */
79*4882a593Smuzhiyun 	MPP12_GIGE,		/* GE_TXD[4] */
80*4882a593Smuzhiyun 	MPP13_GIGE,		/* GE_TXD[5] */
81*4882a593Smuzhiyun 	MPP14_GIGE,		/* GE_TXD[6] */
82*4882a593Smuzhiyun 	MPP15_GIGE,		/* GE_TXD[7] */
83*4882a593Smuzhiyun 	MPP16_GIGE,		/* GE_RXD[4] */
84*4882a593Smuzhiyun 	MPP17_GIGE,		/* GE_RXD[5] */
85*4882a593Smuzhiyun 	MPP18_GIGE,		/* GE_RXD[6] */
86*4882a593Smuzhiyun 	MPP19_GIGE,		/* GE_RXD[7] */
87*4882a593Smuzhiyun 	0,
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
91*4882a593Smuzhiyun 	.phy_addr	= MV643XX_ETH_PHY_NONE,
92*4882a593Smuzhiyun 	.speed		= SPEED_1000,
93*4882a593Smuzhiyun 	.duplex		= DUPLEX_FULL,
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun static struct dsa_chip_data rd88f5181l_ge_switch_chip_data = {
97*4882a593Smuzhiyun 	.port_names[0]	= "lan2",
98*4882a593Smuzhiyun 	.port_names[1]	= "lan1",
99*4882a593Smuzhiyun 	.port_names[2]	= "wan",
100*4882a593Smuzhiyun 	.port_names[3]	= "cpu",
101*4882a593Smuzhiyun 	.port_names[5]	= "lan4",
102*4882a593Smuzhiyun 	.port_names[7]	= "lan3",
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = {
106*4882a593Smuzhiyun 	I2C_BOARD_INFO("ds1338", 0x68),
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun 
rd88f5181l_ge_init(void)109*4882a593Smuzhiyun static void __init rd88f5181l_ge_init(void)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	/*
112*4882a593Smuzhiyun 	 * Setup basic Orion functions. Need to be called early.
113*4882a593Smuzhiyun 	 */
114*4882a593Smuzhiyun 	orion5x_init();
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	orion5x_mpp_conf(rd88f5181l_ge_mpp_modes);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/*
119*4882a593Smuzhiyun 	 * Configure peripherals.
120*4882a593Smuzhiyun 	 */
121*4882a593Smuzhiyun 	orion5x_ehci0_init();
122*4882a593Smuzhiyun 	orion5x_eth_init(&rd88f5181l_ge_eth_data);
123*4882a593Smuzhiyun 	orion5x_eth_switch_init(&rd88f5181l_ge_switch_chip_data);
124*4882a593Smuzhiyun 	orion5x_i2c_init();
125*4882a593Smuzhiyun 	orion5x_uart0_init();
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
128*4882a593Smuzhiyun 				    ORION_MBUS_DEVBUS_BOOT_ATTR,
129*4882a593Smuzhiyun 				    RD88F5181L_GE_NOR_BOOT_BASE,
130*4882a593Smuzhiyun 				    RD88F5181L_GE_NOR_BOOT_SIZE);
131*4882a593Smuzhiyun 	platform_device_register(&rd88f5181l_ge_nor_boot_flash);
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun static int __init
rd88f5181l_ge_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)137*4882a593Smuzhiyun rd88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	int irq;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/*
142*4882a593Smuzhiyun 	 * Check for devices with hard-wired IRQs.
143*4882a593Smuzhiyun 	 */
144*4882a593Smuzhiyun 	irq = orion5x_pci_map_irq(dev, slot, pin);
145*4882a593Smuzhiyun 	if (irq != -1)
146*4882a593Smuzhiyun 		return irq;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	/*
149*4882a593Smuzhiyun 	 * Cardbus slot.
150*4882a593Smuzhiyun 	 */
151*4882a593Smuzhiyun 	if (pin == 1)
152*4882a593Smuzhiyun 		return gpio_to_irq(4);
153*4882a593Smuzhiyun 	else
154*4882a593Smuzhiyun 		return gpio_to_irq(10);
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun static struct hw_pci rd88f5181l_ge_pci __initdata = {
158*4882a593Smuzhiyun 	.nr_controllers	= 2,
159*4882a593Smuzhiyun 	.setup		= orion5x_pci_sys_setup,
160*4882a593Smuzhiyun 	.scan		= orion5x_pci_sys_scan_bus,
161*4882a593Smuzhiyun 	.map_irq	= rd88f5181l_ge_pci_map_irq,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
rd88f5181l_ge_pci_init(void)164*4882a593Smuzhiyun static int __init rd88f5181l_ge_pci_init(void)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	if (machine_is_rd88f5181l_ge()) {
167*4882a593Smuzhiyun 		orion5x_pci_set_cardbus_mode();
168*4882a593Smuzhiyun 		pci_common_init(&rd88f5181l_ge_pci);
169*4882a593Smuzhiyun 	}
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	return 0;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun subsys_initcall(rd88f5181l_ge_pci_init);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
176*4882a593Smuzhiyun 	/* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
177*4882a593Smuzhiyun 	.atag_offset	= 0x100,
178*4882a593Smuzhiyun 	.nr_irqs	= ORION5X_NR_IRQS,
179*4882a593Smuzhiyun 	.init_machine	= rd88f5181l_ge_init,
180*4882a593Smuzhiyun 	.map_io		= orion5x_map_io,
181*4882a593Smuzhiyun 	.init_early	= orion5x_init_early,
182*4882a593Smuzhiyun 	.init_irq	= orion5x_init_irq,
183*4882a593Smuzhiyun 	.init_time	= orion5x_timer_init,
184*4882a593Smuzhiyun 	.fixup		= tag_fixup_mem32,
185*4882a593Smuzhiyun 	.restart	= orion5x_restart,
186*4882a593Smuzhiyun MACHINE_END
187