1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * IRQ definitions for Orion SoC 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 8*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASM_ARCH_IRQS_H 12*4882a593Smuzhiyun #define __ASM_ARCH_IRQS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Orion Main Interrupt Controller 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define IRQ_ORION5X_BRIDGE (1 + 0) 18*4882a593Smuzhiyun #define IRQ_ORION5X_DOORBELL_H2C (1 + 1) 19*4882a593Smuzhiyun #define IRQ_ORION5X_DOORBELL_C2H (1 + 2) 20*4882a593Smuzhiyun #define IRQ_ORION5X_UART0 (1 + 3) 21*4882a593Smuzhiyun #define IRQ_ORION5X_UART1 (1 + 4) 22*4882a593Smuzhiyun #define IRQ_ORION5X_I2C (1 + 5) 23*4882a593Smuzhiyun #define IRQ_ORION5X_GPIO_0_7 (1 + 6) 24*4882a593Smuzhiyun #define IRQ_ORION5X_GPIO_8_15 (1 + 7) 25*4882a593Smuzhiyun #define IRQ_ORION5X_GPIO_16_23 (1 + 8) 26*4882a593Smuzhiyun #define IRQ_ORION5X_GPIO_24_31 (1 + 9) 27*4882a593Smuzhiyun #define IRQ_ORION5X_PCIE0_ERR (1 + 10) 28*4882a593Smuzhiyun #define IRQ_ORION5X_PCIE0_INT (1 + 11) 29*4882a593Smuzhiyun #define IRQ_ORION5X_USB1_CTRL (1 + 12) 30*4882a593Smuzhiyun #define IRQ_ORION5X_DEV_BUS_ERR (1 + 14) 31*4882a593Smuzhiyun #define IRQ_ORION5X_PCI_ERR (1 + 15) 32*4882a593Smuzhiyun #define IRQ_ORION5X_USB_BR_ERR (1 + 16) 33*4882a593Smuzhiyun #define IRQ_ORION5X_USB0_CTRL (1 + 17) 34*4882a593Smuzhiyun #define IRQ_ORION5X_ETH_RX (1 + 18) 35*4882a593Smuzhiyun #define IRQ_ORION5X_ETH_TX (1 + 19) 36*4882a593Smuzhiyun #define IRQ_ORION5X_ETH_MISC (1 + 20) 37*4882a593Smuzhiyun #define IRQ_ORION5X_ETH_SUM (1 + 21) 38*4882a593Smuzhiyun #define IRQ_ORION5X_ETH_ERR (1 + 22) 39*4882a593Smuzhiyun #define IRQ_ORION5X_IDMA_ERR (1 + 23) 40*4882a593Smuzhiyun #define IRQ_ORION5X_IDMA_0 (1 + 24) 41*4882a593Smuzhiyun #define IRQ_ORION5X_IDMA_1 (1 + 25) 42*4882a593Smuzhiyun #define IRQ_ORION5X_IDMA_2 (1 + 26) 43*4882a593Smuzhiyun #define IRQ_ORION5X_IDMA_3 (1 + 27) 44*4882a593Smuzhiyun #define IRQ_ORION5X_CESA (1 + 28) 45*4882a593Smuzhiyun #define IRQ_ORION5X_SATA (1 + 29) 46*4882a593Smuzhiyun #define IRQ_ORION5X_XOR0 (1 + 30) 47*4882a593Smuzhiyun #define IRQ_ORION5X_XOR1 (1 + 31) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * Orion General Purpose Pins 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define IRQ_ORION5X_GPIO_START 33 53*4882a593Smuzhiyun #define NR_GPIO_IRQS 32 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define ORION5X_NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif 59