1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __ARCH_ORION5X_COMMON_H
3*4882a593Smuzhiyun #define __ARCH_ORION5X_COMMON_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/reboot.h>
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun struct dsa_chip_data;
8*4882a593Smuzhiyun struct mv643xx_eth_platform_data;
9*4882a593Smuzhiyun struct mv_sata_platform_data;
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define ORION_MBUS_PCIE_MEM_TARGET 0x04
12*4882a593Smuzhiyun #define ORION_MBUS_PCIE_MEM_ATTR 0x59
13*4882a593Smuzhiyun #define ORION_MBUS_PCIE_IO_TARGET 0x04
14*4882a593Smuzhiyun #define ORION_MBUS_PCIE_IO_ATTR 0x51
15*4882a593Smuzhiyun #define ORION_MBUS_PCIE_WA_TARGET 0x04
16*4882a593Smuzhiyun #define ORION_MBUS_PCIE_WA_ATTR 0x79
17*4882a593Smuzhiyun #define ORION_MBUS_PCI_MEM_TARGET 0x03
18*4882a593Smuzhiyun #define ORION_MBUS_PCI_MEM_ATTR 0x59
19*4882a593Smuzhiyun #define ORION_MBUS_PCI_IO_TARGET 0x03
20*4882a593Smuzhiyun #define ORION_MBUS_PCI_IO_ATTR 0x51
21*4882a593Smuzhiyun #define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01
22*4882a593Smuzhiyun #define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
23*4882a593Smuzhiyun #define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
24*4882a593Smuzhiyun #define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
25*4882a593Smuzhiyun #define ORION_MBUS_SRAM_TARGET 0x09
26*4882a593Smuzhiyun #define ORION_MBUS_SRAM_ATTR 0x00
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * Basic Orion init functions used early by machine-setup.
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun void orion5x_map_io(void);
32*4882a593Smuzhiyun void orion5x_init_early(void);
33*4882a593Smuzhiyun void orion5x_init_irq(void);
34*4882a593Smuzhiyun void orion5x_init(void);
35*4882a593Smuzhiyun void orion5x_id(u32 *dev, u32 *rev, char **dev_name);
36*4882a593Smuzhiyun void clk_init(void);
37*4882a593Smuzhiyun extern int orion5x_tclk;
38*4882a593Smuzhiyun extern void orion5x_timer_init(void);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun void orion5x_setup_wins(void);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun void orion5x_ehci0_init(void);
43*4882a593Smuzhiyun void orion5x_ehci1_init(void);
44*4882a593Smuzhiyun void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
45*4882a593Smuzhiyun void orion5x_eth_switch_init(struct dsa_chip_data *d);
46*4882a593Smuzhiyun void orion5x_i2c_init(void);
47*4882a593Smuzhiyun void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
48*4882a593Smuzhiyun void orion5x_spi_init(void);
49*4882a593Smuzhiyun void orion5x_uart0_init(void);
50*4882a593Smuzhiyun void orion5x_uart1_init(void);
51*4882a593Smuzhiyun void orion5x_xor_init(void);
52*4882a593Smuzhiyun void orion5x_restart(enum reboot_mode, const char *);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * PCIe/PCI functions.
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun struct pci_bus;
58*4882a593Smuzhiyun struct pci_host_bridge;
59*4882a593Smuzhiyun struct pci_sys_data;
60*4882a593Smuzhiyun struct pci_dev;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun void orion5x_pcie_id(u32 *dev, u32 *rev);
63*4882a593Smuzhiyun void orion5x_pci_disable(void);
64*4882a593Smuzhiyun void orion5x_pci_set_cardbus_mode(void);
65*4882a593Smuzhiyun int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
66*4882a593Smuzhiyun int orion5x_pci_sys_scan_bus(int nr, struct pci_host_bridge *bridge);
67*4882a593Smuzhiyun int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun struct tag;
70*4882a593Smuzhiyun extern void __init tag_fixup_mem32(struct tag *, char **);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #ifdef CONFIG_MACH_MSS2_DT
73*4882a593Smuzhiyun extern void mss2_init(void);
74*4882a593Smuzhiyun #else
mss2_init(void)75*4882a593Smuzhiyun static inline void mss2_init(void) {}
76*4882a593Smuzhiyun #endif
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*****************************************************************************
79*4882a593Smuzhiyun * Helpers to access Orion registers
80*4882a593Smuzhiyun ****************************************************************************/
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun * These are not preempt-safe. Locks, if needed, must be taken
83*4882a593Smuzhiyun * care of by the caller.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun #define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r))
86*4882a593Smuzhiyun #define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r))
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #endif
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