1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-orion5x/rd88f5182-setup.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Marvell Orion-NAS Reference Design Setup
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
9*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
10*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #include <linux/gpio.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/pci.h>
17*4882a593Smuzhiyun #include <linux/irq.h>
18*4882a593Smuzhiyun #include <asm/mach-types.h>
19*4882a593Smuzhiyun #include <asm/mach/arch.h>
20*4882a593Smuzhiyun #include <asm/mach/pci.h>
21*4882a593Smuzhiyun #include "common.h"
22*4882a593Smuzhiyun #include "orion5x.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /*****************************************************************************
25*4882a593Smuzhiyun * RD-88F5182 Info
26*4882a593Smuzhiyun ****************************************************************************/
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * PCI
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define RD88F5182_PCI_SLOT0_OFFS 7
33*4882a593Smuzhiyun #define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
34*4882a593Smuzhiyun #define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /*****************************************************************************
37*4882a593Smuzhiyun * PCI
38*4882a593Smuzhiyun ****************************************************************************/
39*4882a593Smuzhiyun
rd88f5182_pci_preinit(void)40*4882a593Smuzhiyun static void __init rd88f5182_pci_preinit(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun int pin;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * Configure PCI GPIO IRQ pins
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
48*4882a593Smuzhiyun if (gpio_request(pin, "PCI IntA") == 0) {
49*4882a593Smuzhiyun if (gpio_direction_input(pin) == 0) {
50*4882a593Smuzhiyun irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
51*4882a593Smuzhiyun } else {
52*4882a593Smuzhiyun printk(KERN_ERR "rd88f5182_pci_preinit failed to "
53*4882a593Smuzhiyun "set_irq_type pin %d\n", pin);
54*4882a593Smuzhiyun gpio_free(pin);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun } else {
57*4882a593Smuzhiyun printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
61*4882a593Smuzhiyun if (gpio_request(pin, "PCI IntB") == 0) {
62*4882a593Smuzhiyun if (gpio_direction_input(pin) == 0) {
63*4882a593Smuzhiyun irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
64*4882a593Smuzhiyun } else {
65*4882a593Smuzhiyun printk(KERN_ERR "rd88f5182_pci_preinit failed to "
66*4882a593Smuzhiyun "set_irq_type pin %d\n", pin);
67*4882a593Smuzhiyun gpio_free(pin);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun } else {
70*4882a593Smuzhiyun printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
rd88f5182_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)74*4882a593Smuzhiyun static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
75*4882a593Smuzhiyun u8 pin)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int irq;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun * Check for devices with hard-wired IRQs.
81*4882a593Smuzhiyun */
82*4882a593Smuzhiyun irq = orion5x_pci_map_irq(dev, slot, pin);
83*4882a593Smuzhiyun if (irq != -1)
84*4882a593Smuzhiyun return irq;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /*
87*4882a593Smuzhiyun * PCI IRQs are connected via GPIOs
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
90*4882a593Smuzhiyun case 0:
91*4882a593Smuzhiyun if (pin == 1)
92*4882a593Smuzhiyun return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
93*4882a593Smuzhiyun else
94*4882a593Smuzhiyun return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
95*4882a593Smuzhiyun default:
96*4882a593Smuzhiyun return -1;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static struct hw_pci rd88f5182_pci __initdata = {
101*4882a593Smuzhiyun .nr_controllers = 2,
102*4882a593Smuzhiyun .preinit = rd88f5182_pci_preinit,
103*4882a593Smuzhiyun .setup = orion5x_pci_sys_setup,
104*4882a593Smuzhiyun .scan = orion5x_pci_sys_scan_bus,
105*4882a593Smuzhiyun .map_irq = rd88f5182_pci_map_irq,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
rd88f5182_pci_init(void)108*4882a593Smuzhiyun static int __init rd88f5182_pci_init(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun if (of_machine_is_compatible("marvell,rd-88f5182-nas"))
111*4882a593Smuzhiyun pci_common_init(&rd88f5182_pci);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return 0;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun subsys_initcall(rd88f5182_pci_init);
117