1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Maxtor Shared Storage II Board Setup
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun #include <asm/mach-types.h>
14*4882a593Smuzhiyun #include <asm/mach/arch.h>
15*4882a593Smuzhiyun #include <asm/mach/pci.h>
16*4882a593Smuzhiyun #include "orion5x.h"
17*4882a593Smuzhiyun #include "bridge-regs.h"
18*4882a593Smuzhiyun #include "common.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*****************************************************************************
21*4882a593Smuzhiyun * Maxtor Shared Storage II Info
22*4882a593Smuzhiyun ****************************************************************************/
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /****************************************************************************
25*4882a593Smuzhiyun * PCI setup
26*4882a593Smuzhiyun ****************************************************************************/
mss2_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)27*4882a593Smuzhiyun static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun int irq;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * Check for devices with hard-wired IRQs.
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun irq = orion5x_pci_map_irq(dev, slot, pin);
35*4882a593Smuzhiyun if (irq != -1)
36*4882a593Smuzhiyun return irq;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return -1;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static struct hw_pci mss2_pci __initdata = {
42*4882a593Smuzhiyun .nr_controllers = 2,
43*4882a593Smuzhiyun .setup = orion5x_pci_sys_setup,
44*4882a593Smuzhiyun .scan = orion5x_pci_sys_scan_bus,
45*4882a593Smuzhiyun .map_irq = mss2_pci_map_irq,
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
mss2_pci_init(void)48*4882a593Smuzhiyun static int __init mss2_pci_init(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun if (machine_is_mss2())
51*4882a593Smuzhiyun pci_common_init(&mss2_pci);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun subsys_initcall(mss2_pci_init);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /*****************************************************************************
58*4882a593Smuzhiyun * MSS2 power off method
59*4882a593Smuzhiyun ****************************************************************************/
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * On the Maxtor Shared Storage II, the shutdown process is the following :
62*4882a593Smuzhiyun * - Userland modifies U-boot env to tell U-boot to go idle at next boot
63*4882a593Smuzhiyun * - The board reboots
64*4882a593Smuzhiyun * - U-boot starts and go into an idle mode until the user press "power"
65*4882a593Smuzhiyun */
mss2_power_off(void)66*4882a593Smuzhiyun static void mss2_power_off(void)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun u32 reg;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * Enable and issue soft reset
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun reg = readl(RSTOUTn_MASK);
74*4882a593Smuzhiyun reg |= 1 << 2;
75*4882a593Smuzhiyun writel(reg, RSTOUTn_MASK);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun reg = readl(CPU_SOFT_RESET);
78*4882a593Smuzhiyun reg |= 1;
79*4882a593Smuzhiyun writel(reg, CPU_SOFT_RESET);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
mss2_init(void)82*4882a593Smuzhiyun void __init mss2_init(void)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun /* register mss2 specific power-off method */
85*4882a593Smuzhiyun pm_power_off = mss2_power_off;
86*4882a593Smuzhiyun }
87