1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #include <linux/platform_data/usb-omap.h> 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* AM35x */ 5*4882a593Smuzhiyun /* USB 2.0 PHY Control */ 6*4882a593Smuzhiyun #define CONF2_PHY_GPIOMODE (1 << 23) 7*4882a593Smuzhiyun #define CONF2_OTGMODE (3 << 14) 8*4882a593Smuzhiyun #define CONF2_NO_OVERRIDE (0 << 14) 9*4882a593Smuzhiyun #define CONF2_FORCE_HOST (1 << 14) 10*4882a593Smuzhiyun #define CONF2_FORCE_DEVICE (2 << 14) 11*4882a593Smuzhiyun #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) 12*4882a593Smuzhiyun #define CONF2_SESENDEN (1 << 13) 13*4882a593Smuzhiyun #define CONF2_VBDTCTEN (1 << 12) 14*4882a593Smuzhiyun #define CONF2_REFFREQ_24MHZ (2 << 8) 15*4882a593Smuzhiyun #define CONF2_REFFREQ_26MHZ (7 << 8) 16*4882a593Smuzhiyun #define CONF2_REFFREQ_13MHZ (6 << 8) 17*4882a593Smuzhiyun #define CONF2_REFFREQ (0xf << 8) 18*4882a593Smuzhiyun #define CONF2_PHYCLKGD (1 << 7) 19*4882a593Smuzhiyun #define CONF2_VBUSSENSE (1 << 6) 20*4882a593Smuzhiyun #define CONF2_PHY_PLLON (1 << 5) 21*4882a593Smuzhiyun #define CONF2_RESET (1 << 4) 22*4882a593Smuzhiyun #define CONF2_PHYPWRDN (1 << 3) 23*4882a593Smuzhiyun #define CONF2_OTGPWRDN (1 << 2) 24*4882a593Smuzhiyun #define CONF2_DATPOL (1 << 1) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* TI81XX specific definitions */ 27*4882a593Smuzhiyun #define USBCTRL0 0x620 28*4882a593Smuzhiyun #define USBSTAT0 0x624 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* TI816X PHY controls bits */ 31*4882a593Smuzhiyun #define TI816X_USBPHY0_NORMAL_MODE (1 << 0) 32*4882a593Smuzhiyun #define TI816X_USBPHY_REFCLK_OSC (1 << 8) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* TI814X PHY controls bits */ 35*4882a593Smuzhiyun #define USBPHY_CM_PWRDN (1 << 0) 36*4882a593Smuzhiyun #define USBPHY_OTG_PWRDN (1 << 1) 37*4882a593Smuzhiyun #define USBPHY_CHGDET_DIS (1 << 2) 38*4882a593Smuzhiyun #define USBPHY_CHGDET_RSTRT (1 << 3) 39*4882a593Smuzhiyun #define USBPHY_SRCONDM (1 << 4) 40*4882a593Smuzhiyun #define USBPHY_SINKONDP (1 << 5) 41*4882a593Smuzhiyun #define USBPHY_CHGISINK_EN (1 << 6) 42*4882a593Smuzhiyun #define USBPHY_CHGVSRC_EN (1 << 7) 43*4882a593Smuzhiyun #define USBPHY_DMPULLUP (1 << 8) 44*4882a593Smuzhiyun #define USBPHY_DPPULLUP (1 << 9) 45*4882a593Smuzhiyun #define USBPHY_CDET_EXTCTL (1 << 10) 46*4882a593Smuzhiyun #define USBPHY_GPIO_MODE (1 << 12) 47*4882a593Smuzhiyun #define USBPHY_DPOPBUFCTL (1 << 13) 48*4882a593Smuzhiyun #define USBPHY_DMOPBUFCTL (1 << 14) 49*4882a593Smuzhiyun #define USBPHY_DPINPUT (1 << 15) 50*4882a593Smuzhiyun #define USBPHY_DMINPUT (1 << 16) 51*4882a593Smuzhiyun #define USBPHY_DPGPIO_PD (1 << 17) 52*4882a593Smuzhiyun #define USBPHY_DMGPIO_PD (1 << 18) 53*4882a593Smuzhiyun #define USBPHY_OTGVDET_EN (1 << 19) 54*4882a593Smuzhiyun #define USBPHY_OTGSESSEND_EN (1 << 20) 55*4882a593Smuzhiyun #define USBPHY_DATA_POLARITY (1 << 23) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct usbhs_phy_data { 58*4882a593Smuzhiyun int port; /* 1 indexed port number */ 59*4882a593Smuzhiyun int reset_gpio; 60*4882a593Smuzhiyun int vcc_gpio; 61*4882a593Smuzhiyun bool vcc_polarity; /* 1 active high, 0 active low */ 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun extern void usb_musb_init(struct omap_musb_board_data *board_data); 65*4882a593Smuzhiyun extern void usbhs_init(struct usbhs_omap_platform_data *pdata); 66*4882a593Smuzhiyun extern int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun extern void am35x_musb_reset(void); 69*4882a593Smuzhiyun extern void am35x_musb_phy_power(u8 on); 70*4882a593Smuzhiyun extern void am35x_musb_clear_irq(void); 71*4882a593Smuzhiyun extern void am35x_set_mode(u8 musb_mode); 72