1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP54XX SCRM registers and bitfields 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 10*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 11*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 12*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 13*4882a593Smuzhiyun * up-to-date with the file contents. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H 17*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define OMAP5_SCRM_BASE 0x4ae0a000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define OMAP54XX_SCRM_REGADDR(reg) \ 22*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg)) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* SCRM */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* SCRM.SCRM register offsets */ 27*4882a593Smuzhiyun #define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000 28*4882a593Smuzhiyun #define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000) 29*4882a593Smuzhiyun #define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100 30*4882a593Smuzhiyun #define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100) 31*4882a593Smuzhiyun #define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104 32*4882a593Smuzhiyun #define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104) 33*4882a593Smuzhiyun #define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110 34*4882a593Smuzhiyun #define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110) 35*4882a593Smuzhiyun #define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118 36*4882a593Smuzhiyun #define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118) 37*4882a593Smuzhiyun #define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c 38*4882a593Smuzhiyun #define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c) 39*4882a593Smuzhiyun #define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200 40*4882a593Smuzhiyun #define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200) 41*4882a593Smuzhiyun #define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204 42*4882a593Smuzhiyun #define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204) 43*4882a593Smuzhiyun #define OMAP5_SCRM_PWRREQ_OFFSET 0x0208 44*4882a593Smuzhiyun #define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208) 45*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210 46*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210) 47*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214 48*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214) 49*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218 50*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218) 51*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c 52*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c) 53*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220 54*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220) 55*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224 56*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224) 57*4882a593Smuzhiyun #define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234 58*4882a593Smuzhiyun #define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234) 59*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310 60*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310) 61*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314 62*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314) 63*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318 64*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318) 65*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c 66*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c) 67*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320 68*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320) 69*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324 70*4882a593Smuzhiyun #define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324) 71*4882a593Smuzhiyun #define OMAP5_SCRM_RSTTIME_OFFSET 0x0400 72*4882a593Smuzhiyun #define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400) 73*4882a593Smuzhiyun #define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418 74*4882a593Smuzhiyun #define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418) 75*4882a593Smuzhiyun #define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c 76*4882a593Smuzhiyun #define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c) 77*4882a593Smuzhiyun #define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 78*4882a593Smuzhiyun #define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420) 79*4882a593Smuzhiyun #define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510 80*4882a593Smuzhiyun #define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510) 81*4882a593Smuzhiyun #define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514 82*4882a593Smuzhiyun #define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514) 83*4882a593Smuzhiyun #define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518 84*4882a593Smuzhiyun #define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518) 85*4882a593Smuzhiyun #define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c 86*4882a593Smuzhiyun #define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, 90*4882a593Smuzhiyun * AUXCLKREQ5, D2DCLKREQ 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #define OMAP5_ACCURACY_SHIFT 1 93*4882a593Smuzhiyun #define OMAP5_ACCURACY_WIDTH 0x1 94*4882a593Smuzhiyun #define OMAP5_ACCURACY_MASK (1 << 1) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* Used by APEWARMRSTST */ 97*4882a593Smuzhiyun #define OMAP5_APEWARMRSTST_SHIFT 1 98*4882a593Smuzhiyun #define OMAP5_APEWARMRSTST_WIDTH 0x1 99*4882a593Smuzhiyun #define OMAP5_APEWARMRSTST_MASK (1 << 1) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ 102*4882a593Smuzhiyun #define OMAP5_CLKDIV_SHIFT 16 103*4882a593Smuzhiyun #define OMAP5_CLKDIV_WIDTH 0x4 104*4882a593Smuzhiyun #define OMAP5_CLKDIV_MASK (0xf << 16) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Used by D2DCLKM, MODEMCLKM */ 107*4882a593Smuzhiyun #define OMAP5_CLK_32KHZ_SHIFT 0 108*4882a593Smuzhiyun #define OMAP5_CLK_32KHZ_WIDTH 0x1 109*4882a593Smuzhiyun #define OMAP5_CLK_32KHZ_MASK (1 << 0) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* Used by D2DRSTCTRL, MODEMRSTCTRL */ 112*4882a593Smuzhiyun #define OMAP5_COLDRST_SHIFT 0 113*4882a593Smuzhiyun #define OMAP5_COLDRST_WIDTH 0x1 114*4882a593Smuzhiyun #define OMAP5_COLDRST_MASK (1 << 0) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* Used by D2DWARMRSTST */ 117*4882a593Smuzhiyun #define OMAP5_D2DWARMRSTST_SHIFT 3 118*4882a593Smuzhiyun #define OMAP5_D2DWARMRSTST_WIDTH 0x1 119*4882a593Smuzhiyun #define OMAP5_D2DWARMRSTST_MASK (1 << 3) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* Used by AUXCLK0 */ 122*4882a593Smuzhiyun #define OMAP5_DISABLECLK_SHIFT 9 123*4882a593Smuzhiyun #define OMAP5_DISABLECLK_WIDTH 0x1 124*4882a593Smuzhiyun #define OMAP5_DISABLECLK_MASK (1 << 9) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* Used by CLKSETUPTIME */ 127*4882a593Smuzhiyun #define OMAP5_DOWNTIME_SHIFT 16 128*4882a593Smuzhiyun #define OMAP5_DOWNTIME_WIDTH 0x6 129*4882a593Smuzhiyun #define OMAP5_DOWNTIME_MASK (0x3f << 16) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ 132*4882a593Smuzhiyun #define OMAP5_ENABLE_SHIFT 8 133*4882a593Smuzhiyun #define OMAP5_ENABLE_WIDTH 0x1 134*4882a593Smuzhiyun #define OMAP5_ENABLE_MASK (1 << 8) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Renamed from ENABLE Used by EXTPWRONRSTCTRL */ 137*4882a593Smuzhiyun #define OMAP5_ENABLE_0_0_SHIFT 0 138*4882a593Smuzhiyun #define OMAP5_ENABLE_0_0_WIDTH 0x1 139*4882a593Smuzhiyun #define OMAP5_ENABLE_0_0_MASK (1 << 0) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* Used by ALTCLKSRC */ 142*4882a593Smuzhiyun #define OMAP5_ENABLE_EXT_SHIFT 3 143*4882a593Smuzhiyun #define OMAP5_ENABLE_EXT_WIDTH 0x1 144*4882a593Smuzhiyun #define OMAP5_ENABLE_EXT_MASK (1 << 3) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Used by ALTCLKSRC */ 147*4882a593Smuzhiyun #define OMAP5_ENABLE_INT_SHIFT 2 148*4882a593Smuzhiyun #define OMAP5_ENABLE_INT_WIDTH 0x1 149*4882a593Smuzhiyun #define OMAP5_ENABLE_INT_MASK (1 << 2) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* Used by EXTWARMRSTST */ 152*4882a593Smuzhiyun #define OMAP5_EXTWARMRSTST_SHIFT 0 153*4882a593Smuzhiyun #define OMAP5_EXTWARMRSTST_WIDTH 0x1 154*4882a593Smuzhiyun #define OMAP5_EXTWARMRSTST_MASK (1 << 0) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* 157*4882a593Smuzhiyun * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, 158*4882a593Smuzhiyun * AUXCLKREQ5 159*4882a593Smuzhiyun */ 160*4882a593Smuzhiyun #define OMAP5_MAPPING_SHIFT 2 161*4882a593Smuzhiyun #define OMAP5_MAPPING_WIDTH 0x3 162*4882a593Smuzhiyun #define OMAP5_MAPPING_MASK (0x7 << 2) 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* Used by ALTCLKSRC */ 165*4882a593Smuzhiyun #define OMAP5_MODE_SHIFT 0 166*4882a593Smuzhiyun #define OMAP5_MODE_WIDTH 0x2 167*4882a593Smuzhiyun #define OMAP5_MODE_MASK (0x3 << 0) 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* Used by MODEMWARMRSTST */ 170*4882a593Smuzhiyun #define OMAP5_MODEMWARMRSTST_SHIFT 2 171*4882a593Smuzhiyun #define OMAP5_MODEMWARMRSTST_WIDTH 0x1 172*4882a593Smuzhiyun #define OMAP5_MODEMWARMRSTST_MASK (1 << 2) 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun /* 175*4882a593Smuzhiyun * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5, 176*4882a593Smuzhiyun * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5, 177*4882a593Smuzhiyun * D2DCLKREQ, EXTCLKREQ, PWRREQ 178*4882a593Smuzhiyun */ 179*4882a593Smuzhiyun #define OMAP5_POLARITY_SHIFT 0 180*4882a593Smuzhiyun #define OMAP5_POLARITY_WIDTH 0x1 181*4882a593Smuzhiyun #define OMAP5_POLARITY_MASK (1 << 0) 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* Used by EXTPWRONRSTCTRL */ 184*4882a593Smuzhiyun #define OMAP5_PWRONRST_SHIFT 1 185*4882a593Smuzhiyun #define OMAP5_PWRONRST_WIDTH 0x1 186*4882a593Smuzhiyun #define OMAP5_PWRONRST_MASK (1 << 1) 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* Used by REVISION_SCRM */ 189*4882a593Smuzhiyun #define OMAP5_REV_SHIFT 0 190*4882a593Smuzhiyun #define OMAP5_REV_WIDTH 0x8 191*4882a593Smuzhiyun #define OMAP5_REV_MASK (0xff << 0) 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* Used by RSTTIME */ 194*4882a593Smuzhiyun #define OMAP5_RSTTIME_SHIFT 0 195*4882a593Smuzhiyun #define OMAP5_RSTTIME_WIDTH 0x4 196*4882a593Smuzhiyun #define OMAP5_RSTTIME_MASK (0xf << 0) 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* Used by CLKSETUPTIME */ 199*4882a593Smuzhiyun #define OMAP5_SETUPTIME_SHIFT 0 200*4882a593Smuzhiyun #define OMAP5_SETUPTIME_WIDTH 0xc 201*4882a593Smuzhiyun #define OMAP5_SETUPTIME_MASK (0xfff << 0) 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* Used by PMICSETUPTIME */ 204*4882a593Smuzhiyun #define OMAP5_SLEEPTIME_SHIFT 0 205*4882a593Smuzhiyun #define OMAP5_SLEEPTIME_WIDTH 0x6 206*4882a593Smuzhiyun #define OMAP5_SLEEPTIME_MASK (0x3f << 0) 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ 209*4882a593Smuzhiyun #define OMAP5_SRCSELECT_SHIFT 1 210*4882a593Smuzhiyun #define OMAP5_SRCSELECT_WIDTH 0x2 211*4882a593Smuzhiyun #define OMAP5_SRCSELECT_MASK (0x3 << 1) 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun /* Used by D2DCLKM */ 214*4882a593Smuzhiyun #define OMAP5_SYSCLK_SHIFT 1 215*4882a593Smuzhiyun #define OMAP5_SYSCLK_WIDTH 0x1 216*4882a593Smuzhiyun #define OMAP5_SYSCLK_MASK (1 << 1) 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* Used by PMICSETUPTIME */ 219*4882a593Smuzhiyun #define OMAP5_WAKEUPTIME_SHIFT 16 220*4882a593Smuzhiyun #define OMAP5_WAKEUPTIME_WIDTH 0x6 221*4882a593Smuzhiyun #define OMAP5_WAKEUPTIME_MASK (0x3f << 16) 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* Used by D2DRSTCTRL, MODEMRSTCTRL */ 224*4882a593Smuzhiyun #define OMAP5_WARMRST_SHIFT 1 225*4882a593Smuzhiyun #define OMAP5_WARMRST_WIDTH 0x1 226*4882a593Smuzhiyun #define OMAP5_WARMRST_MASK (1 << 1) 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun #endif 229