1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP44xx SCRM registers and bitfields 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 Texas Instruments, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 10*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 11*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 12*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 13*4882a593Smuzhiyun * up-to-date with the file contents. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H 17*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define OMAP4_SCRM_BASE 0x4a30a000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define OMAP44XX_SCRM_REGADDR(reg) \ 22*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg)) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Registers offset */ 25*4882a593Smuzhiyun #define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000 26*4882a593Smuzhiyun #define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000) 27*4882a593Smuzhiyun #define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100 28*4882a593Smuzhiyun #define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100) 29*4882a593Smuzhiyun #define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104 30*4882a593Smuzhiyun #define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104) 31*4882a593Smuzhiyun #define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110 32*4882a593Smuzhiyun #define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110) 33*4882a593Smuzhiyun #define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118 34*4882a593Smuzhiyun #define OMAP4_SCRM_MODEMCLKM OMAP44XX_SCRM_REGADDR(0x0118) 35*4882a593Smuzhiyun #define OMAP4_SCRM_D2DCLKM_OFFSET 0x011c 36*4882a593Smuzhiyun #define OMAP4_SCRM_D2DCLKM OMAP44XX_SCRM_REGADDR(0x011c) 37*4882a593Smuzhiyun #define OMAP4_SCRM_EXTCLKREQ_OFFSET 0x0200 38*4882a593Smuzhiyun #define OMAP4_SCRM_EXTCLKREQ OMAP44XX_SCRM_REGADDR(0x0200) 39*4882a593Smuzhiyun #define OMAP4_SCRM_ACCCLKREQ_OFFSET 0x0204 40*4882a593Smuzhiyun #define OMAP4_SCRM_ACCCLKREQ OMAP44XX_SCRM_REGADDR(0x0204) 41*4882a593Smuzhiyun #define OMAP4_SCRM_PWRREQ_OFFSET 0x0208 42*4882a593Smuzhiyun #define OMAP4_SCRM_PWRREQ OMAP44XX_SCRM_REGADDR(0x0208) 43*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ0_OFFSET 0x0210 44*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ0 OMAP44XX_SCRM_REGADDR(0x0210) 45*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ1_OFFSET 0x0214 46*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ1 OMAP44XX_SCRM_REGADDR(0x0214) 47*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ2_OFFSET 0x0218 48*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ2 OMAP44XX_SCRM_REGADDR(0x0218) 49*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ3_OFFSET 0x021c 50*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ3 OMAP44XX_SCRM_REGADDR(0x021c) 51*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ4_OFFSET 0x0220 52*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ4 OMAP44XX_SCRM_REGADDR(0x0220) 53*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ5_OFFSET 0x0224 54*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLKREQ5 OMAP44XX_SCRM_REGADDR(0x0224) 55*4882a593Smuzhiyun #define OMAP4_SCRM_D2DCLKREQ_OFFSET 0x0234 56*4882a593Smuzhiyun #define OMAP4_SCRM_D2DCLKREQ OMAP44XX_SCRM_REGADDR(0x0234) 57*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK0_OFFSET 0x0310 58*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK0 OMAP44XX_SCRM_REGADDR(0x0310) 59*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK1_OFFSET 0x0314 60*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK1 OMAP44XX_SCRM_REGADDR(0x0314) 61*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK2_OFFSET 0x0318 62*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK2 OMAP44XX_SCRM_REGADDR(0x0318) 63*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK3_OFFSET 0x031c 64*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK3 OMAP44XX_SCRM_REGADDR(0x031c) 65*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK4_OFFSET 0x0320 66*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK4 OMAP44XX_SCRM_REGADDR(0x0320) 67*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK5_OFFSET 0x0324 68*4882a593Smuzhiyun #define OMAP4_SCRM_AUXCLK5 OMAP44XX_SCRM_REGADDR(0x0324) 69*4882a593Smuzhiyun #define OMAP4_SCRM_RSTTIME_OFFSET 0x0400 70*4882a593Smuzhiyun #define OMAP4_SCRM_RSTTIME OMAP44XX_SCRM_REGADDR(0x0400) 71*4882a593Smuzhiyun #define OMAP4_SCRM_MODEMRSTCTRL_OFFSET 0x0418 72*4882a593Smuzhiyun #define OMAP4_SCRM_MODEMRSTCTRL OMAP44XX_SCRM_REGADDR(0x0418) 73*4882a593Smuzhiyun #define OMAP4_SCRM_D2DRSTCTRL_OFFSET 0x041c 74*4882a593Smuzhiyun #define OMAP4_SCRM_D2DRSTCTRL OMAP44XX_SCRM_REGADDR(0x041c) 75*4882a593Smuzhiyun #define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 76*4882a593Smuzhiyun #define OMAP4_SCRM_EXTPWRONRSTCTRL OMAP44XX_SCRM_REGADDR(0x0420) 77*4882a593Smuzhiyun #define OMAP4_SCRM_EXTWARMRSTST_OFFSET 0x0510 78*4882a593Smuzhiyun #define OMAP4_SCRM_EXTWARMRSTST OMAP44XX_SCRM_REGADDR(0x0510) 79*4882a593Smuzhiyun #define OMAP4_SCRM_APEWARMRSTST_OFFSET 0x0514 80*4882a593Smuzhiyun #define OMAP4_SCRM_APEWARMRSTST OMAP44XX_SCRM_REGADDR(0x0514) 81*4882a593Smuzhiyun #define OMAP4_SCRM_MODEMWARMRSTST_OFFSET 0x0518 82*4882a593Smuzhiyun #define OMAP4_SCRM_MODEMWARMRSTST OMAP44XX_SCRM_REGADDR(0x0518) 83*4882a593Smuzhiyun #define OMAP4_SCRM_D2DWARMRSTST_OFFSET 0x051c 84*4882a593Smuzhiyun #define OMAP4_SCRM_D2DWARMRSTST OMAP44XX_SCRM_REGADDR(0x051c) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Registers shifts and masks */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* REVISION_SCRM */ 89*4882a593Smuzhiyun #define OMAP4_REV_SHIFT 0 90*4882a593Smuzhiyun #define OMAP4_REV_MASK (0xff << 0) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* CLKSETUPTIME */ 93*4882a593Smuzhiyun #define OMAP4_DOWNTIME_SHIFT 16 94*4882a593Smuzhiyun #define OMAP4_DOWNTIME_MASK (0x3f << 16) 95*4882a593Smuzhiyun #define OMAP4_SETUPTIME_SHIFT 0 96*4882a593Smuzhiyun #define OMAP4_SETUPTIME_MASK (0xfff << 0) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* PMICSETUPTIME */ 99*4882a593Smuzhiyun #define OMAP4_WAKEUPTIME_SHIFT 16 100*4882a593Smuzhiyun #define OMAP4_WAKEUPTIME_MASK (0x3f << 16) 101*4882a593Smuzhiyun #define OMAP4_SLEEPTIME_SHIFT 0 102*4882a593Smuzhiyun #define OMAP4_SLEEPTIME_MASK (0x3f << 0) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* ALTCLKSRC */ 105*4882a593Smuzhiyun #define OMAP4_ENABLE_EXT_SHIFT 3 106*4882a593Smuzhiyun #define OMAP4_ENABLE_EXT_MASK (1 << 3) 107*4882a593Smuzhiyun #define OMAP4_ENABLE_INT_SHIFT 2 108*4882a593Smuzhiyun #define OMAP4_ENABLE_INT_MASK (1 << 2) 109*4882a593Smuzhiyun #define OMAP4_ALTCLKSRC_MODE_SHIFT 0 110*4882a593Smuzhiyun #define OMAP4_ALTCLKSRC_MODE_MASK (0x3 << 0) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* MODEMCLKM */ 113*4882a593Smuzhiyun #define OMAP4_CLK_32KHZ_SHIFT 0 114*4882a593Smuzhiyun #define OMAP4_CLK_32KHZ_MASK (1 << 0) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* D2DCLKM */ 117*4882a593Smuzhiyun #define OMAP4_SYSCLK_SHIFT 1 118*4882a593Smuzhiyun #define OMAP4_SYSCLK_MASK (1 << 1) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* EXTCLKREQ */ 121*4882a593Smuzhiyun #define OMAP4_POLARITY_SHIFT 0 122*4882a593Smuzhiyun #define OMAP4_POLARITY_MASK (1 << 0) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* AUXCLKREQ0 */ 125*4882a593Smuzhiyun #define OMAP4_MAPPING_SHIFT 2 126*4882a593Smuzhiyun #define OMAP4_MAPPING_MASK (0x7 << 2) 127*4882a593Smuzhiyun #define OMAP4_MAPPING_WIDTH 3 128*4882a593Smuzhiyun #define OMAP4_ACCURACY_SHIFT 1 129*4882a593Smuzhiyun #define OMAP4_ACCURACY_MASK (1 << 1) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* AUXCLK0 */ 132*4882a593Smuzhiyun #define OMAP4_CLKDIV_SHIFT 16 133*4882a593Smuzhiyun #define OMAP4_CLKDIV_MASK (0xf << 16) 134*4882a593Smuzhiyun #define OMAP4_CLKDIV_WIDTH 4 135*4882a593Smuzhiyun #define OMAP4_DISABLECLK_SHIFT 9 136*4882a593Smuzhiyun #define OMAP4_DISABLECLK_MASK (1 << 9) 137*4882a593Smuzhiyun #define OMAP4_ENABLE_SHIFT 8 138*4882a593Smuzhiyun #define OMAP4_ENABLE_MASK (1 << 8) 139*4882a593Smuzhiyun #define OMAP4_SRCSELECT_SHIFT 1 140*4882a593Smuzhiyun #define OMAP4_SRCSELECT_MASK (0x3 << 1) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* RSTTIME */ 143*4882a593Smuzhiyun #define OMAP4_RSTTIME_SHIFT 0 144*4882a593Smuzhiyun #define OMAP4_RSTTIME_MASK (0xf << 0) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* MODEMRSTCTRL */ 147*4882a593Smuzhiyun #define OMAP4_WARMRST_SHIFT 1 148*4882a593Smuzhiyun #define OMAP4_WARMRST_MASK (1 << 1) 149*4882a593Smuzhiyun #define OMAP4_COLDRST_SHIFT 0 150*4882a593Smuzhiyun #define OMAP4_COLDRST_MASK (1 << 0) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* EXTPWRONRSTCTRL */ 153*4882a593Smuzhiyun #define OMAP4_PWRONRST_SHIFT 1 154*4882a593Smuzhiyun #define OMAP4_PWRONRST_MASK (1 << 1) 155*4882a593Smuzhiyun #define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT 0 156*4882a593Smuzhiyun #define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK (1 << 0) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* EXTWARMRSTST */ 159*4882a593Smuzhiyun #define OMAP4_EXTWARMRSTST_SHIFT 0 160*4882a593Smuzhiyun #define OMAP4_EXTWARMRSTST_MASK (1 << 0) 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* APEWARMRSTST */ 163*4882a593Smuzhiyun #define OMAP4_APEWARMRSTST_SHIFT 1 164*4882a593Smuzhiyun #define OMAP4_APEWARMRSTST_MASK (1 << 1) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* MODEMWARMRSTST */ 167*4882a593Smuzhiyun #define OMAP4_MODEMWARMRSTST_SHIFT 2 168*4882a593Smuzhiyun #define OMAP4_MODEMWARMRSTST_MASK (1 << 2) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* D2DWARMRSTST */ 171*4882a593Smuzhiyun #define OMAP4_D2DWARMRSTST_SHIFT 3 172*4882a593Smuzhiyun #define OMAP4_D2DWARMRSTST_MASK (1 << 3) 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #endif 175