1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP44xx PRM instance offset macros 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009-2011 Texas Instruments, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2009-2010 Nokia Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Paul Walmsley (paul@pwsan.com) 9*4882a593Smuzhiyun * Rajendra Nayak (rnayak@ti.com) 10*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 13*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 14*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 15*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 16*4882a593Smuzhiyun * up-to-date with the file contents. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 19*4882a593Smuzhiyun * or "OMAP4430". 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H 23*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #include "prm44xx_54xx.h" 26*4882a593Smuzhiyun #include "prm.h" 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define OMAP4430_PRM_BASE 0x4a306000 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define OMAP44XX_PRM_REGADDR(inst, reg) \ 31*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* PRM instances */ 35*4882a593Smuzhiyun #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000 36*4882a593Smuzhiyun #define OMAP4430_PRM_CKGEN_INST 0x0100 37*4882a593Smuzhiyun #define OMAP4430_PRM_MPU_INST 0x0300 38*4882a593Smuzhiyun #define OMAP4430_PRM_TESLA_INST 0x0400 39*4882a593Smuzhiyun #define OMAP4430_PRM_ABE_INST 0x0500 40*4882a593Smuzhiyun #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600 41*4882a593Smuzhiyun #define OMAP4430_PRM_CORE_INST 0x0700 42*4882a593Smuzhiyun #define OMAP4430_PRM_IVAHD_INST 0x0f00 43*4882a593Smuzhiyun #define OMAP4430_PRM_CAM_INST 0x1000 44*4882a593Smuzhiyun #define OMAP4430_PRM_DSS_INST 0x1100 45*4882a593Smuzhiyun #define OMAP4430_PRM_GFX_INST 0x1200 46*4882a593Smuzhiyun #define OMAP4430_PRM_L3INIT_INST 0x1300 47*4882a593Smuzhiyun #define OMAP4430_PRM_L4PER_INST 0x1400 48*4882a593Smuzhiyun #define OMAP4430_PRM_CEFUSE_INST 0x1600 49*4882a593Smuzhiyun #define OMAP4430_PRM_WKUP_INST 0x1700 50*4882a593Smuzhiyun #define OMAP4430_PRM_WKUP_CM_INST 0x1800 51*4882a593Smuzhiyun #define OMAP4430_PRM_EMU_INST 0x1900 52*4882a593Smuzhiyun #define OMAP4430_PRM_EMU_CM_INST 0x1a00 53*4882a593Smuzhiyun #define OMAP4430_PRM_DEVICE_INST 0x1b00 54*4882a593Smuzhiyun #define OMAP4430_PRM_INSTR_INST 0x1f00 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* PRM clockdomain register offsets (from instance start) */ 57*4882a593Smuzhiyun #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 58*4882a593Smuzhiyun #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* OMAP4 specific register offsets */ 61*4882a593Smuzhiyun #define OMAP4_RM_RSTCTRL 0x0000 62*4882a593Smuzhiyun #define OMAP4_RM_RSTST 0x0004 63*4882a593Smuzhiyun #define OMAP4_RM_RSTTIME 0x0008 64*4882a593Smuzhiyun #define OMAP4_PM_PWSTCTRL 0x0000 65*4882a593Smuzhiyun #define OMAP4_PM_PWSTST 0x0004 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* PRM */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* PRM.OCP_SOCKET_PRM register offsets */ 71*4882a593Smuzhiyun #define OMAP4_REVISION_PRM_OFFSET 0x0000 72*4882a593Smuzhiyun #define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000) 73*4882a593Smuzhiyun #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 74*4882a593Smuzhiyun #define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010) 75*4882a593Smuzhiyun #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 76*4882a593Smuzhiyun #define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014) 77*4882a593Smuzhiyun #define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 78*4882a593Smuzhiyun #define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018) 79*4882a593Smuzhiyun #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 80*4882a593Smuzhiyun #define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c) 81*4882a593Smuzhiyun #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020 82*4882a593Smuzhiyun #define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020) 83*4882a593Smuzhiyun #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028 84*4882a593Smuzhiyun #define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028) 85*4882a593Smuzhiyun #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030 86*4882a593Smuzhiyun #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030) 87*4882a593Smuzhiyun #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 88*4882a593Smuzhiyun #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038) 89*4882a593Smuzhiyun #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 90*4882a593Smuzhiyun #define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* PRM.CKGEN_PRM register offsets */ 93*4882a593Smuzhiyun #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 94*4882a593Smuzhiyun #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000) 95*4882a593Smuzhiyun #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 96*4882a593Smuzhiyun #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008) 97*4882a593Smuzhiyun #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c 98*4882a593Smuzhiyun #define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c) 99*4882a593Smuzhiyun #define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010 100*4882a593Smuzhiyun #define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* PRM.MPU_PRM register offsets */ 103*4882a593Smuzhiyun #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000 104*4882a593Smuzhiyun #define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000) 105*4882a593Smuzhiyun #define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004 106*4882a593Smuzhiyun #define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004) 107*4882a593Smuzhiyun #define OMAP4_RM_MPU_RSTST_OFFSET 0x0014 108*4882a593Smuzhiyun #define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014) 109*4882a593Smuzhiyun #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 110*4882a593Smuzhiyun #define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* PRM.TESLA_PRM register offsets */ 113*4882a593Smuzhiyun #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000 114*4882a593Smuzhiyun #define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000) 115*4882a593Smuzhiyun #define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004 116*4882a593Smuzhiyun #define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004) 117*4882a593Smuzhiyun #define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010 118*4882a593Smuzhiyun #define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010) 119*4882a593Smuzhiyun #define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014 120*4882a593Smuzhiyun #define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014) 121*4882a593Smuzhiyun #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024 122*4882a593Smuzhiyun #define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* PRM.ABE_PRM register offsets */ 125*4882a593Smuzhiyun #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000 126*4882a593Smuzhiyun #define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000) 127*4882a593Smuzhiyun #define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004 128*4882a593Smuzhiyun #define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004) 129*4882a593Smuzhiyun #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c 130*4882a593Smuzhiyun #define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c) 131*4882a593Smuzhiyun #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030 132*4882a593Smuzhiyun #define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030) 133*4882a593Smuzhiyun #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034 134*4882a593Smuzhiyun #define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034) 135*4882a593Smuzhiyun #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 136*4882a593Smuzhiyun #define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038) 137*4882a593Smuzhiyun #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c 138*4882a593Smuzhiyun #define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c) 139*4882a593Smuzhiyun #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 140*4882a593Smuzhiyun #define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040) 141*4882a593Smuzhiyun #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 142*4882a593Smuzhiyun #define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044) 143*4882a593Smuzhiyun #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 144*4882a593Smuzhiyun #define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048) 145*4882a593Smuzhiyun #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c 146*4882a593Smuzhiyun #define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c) 147*4882a593Smuzhiyun #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 148*4882a593Smuzhiyun #define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050) 149*4882a593Smuzhiyun #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 150*4882a593Smuzhiyun #define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054) 151*4882a593Smuzhiyun #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 152*4882a593Smuzhiyun #define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058) 153*4882a593Smuzhiyun #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c 154*4882a593Smuzhiyun #define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c) 155*4882a593Smuzhiyun #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060 156*4882a593Smuzhiyun #define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060) 157*4882a593Smuzhiyun #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064 158*4882a593Smuzhiyun #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064) 159*4882a593Smuzhiyun #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 160*4882a593Smuzhiyun #define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068) 161*4882a593Smuzhiyun #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c 162*4882a593Smuzhiyun #define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c) 163*4882a593Smuzhiyun #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 164*4882a593Smuzhiyun #define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070) 165*4882a593Smuzhiyun #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 166*4882a593Smuzhiyun #define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074) 167*4882a593Smuzhiyun #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 168*4882a593Smuzhiyun #define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078) 169*4882a593Smuzhiyun #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c 170*4882a593Smuzhiyun #define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c) 171*4882a593Smuzhiyun #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 172*4882a593Smuzhiyun #define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080) 173*4882a593Smuzhiyun #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 174*4882a593Smuzhiyun #define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084) 175*4882a593Smuzhiyun #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088 176*4882a593Smuzhiyun #define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088) 177*4882a593Smuzhiyun #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c 178*4882a593Smuzhiyun #define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* PRM.ALWAYS_ON_PRM register offsets */ 181*4882a593Smuzhiyun #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024 182*4882a593Smuzhiyun #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024) 183*4882a593Smuzhiyun #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028 184*4882a593Smuzhiyun #define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028) 185*4882a593Smuzhiyun #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c 186*4882a593Smuzhiyun #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c) 187*4882a593Smuzhiyun #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030 188*4882a593Smuzhiyun #define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030) 189*4882a593Smuzhiyun #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034 190*4882a593Smuzhiyun #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034) 191*4882a593Smuzhiyun #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038 192*4882a593Smuzhiyun #define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038) 193*4882a593Smuzhiyun #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c 194*4882a593Smuzhiyun #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c) 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* PRM.CORE_PRM register offsets */ 197*4882a593Smuzhiyun #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000 198*4882a593Smuzhiyun #define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000) 199*4882a593Smuzhiyun #define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004 200*4882a593Smuzhiyun #define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004) 201*4882a593Smuzhiyun #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024 202*4882a593Smuzhiyun #define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024) 203*4882a593Smuzhiyun #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124 204*4882a593Smuzhiyun #define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124) 205*4882a593Smuzhiyun #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c 206*4882a593Smuzhiyun #define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c) 207*4882a593Smuzhiyun #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134 208*4882a593Smuzhiyun #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134) 209*4882a593Smuzhiyun #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210 210*4882a593Smuzhiyun #define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210) 211*4882a593Smuzhiyun #define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214 212*4882a593Smuzhiyun #define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214) 213*4882a593Smuzhiyun #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224 214*4882a593Smuzhiyun #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224) 215*4882a593Smuzhiyun #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324 216*4882a593Smuzhiyun #define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324) 217*4882a593Smuzhiyun #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424 218*4882a593Smuzhiyun #define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424) 219*4882a593Smuzhiyun #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c 220*4882a593Smuzhiyun #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c) 221*4882a593Smuzhiyun #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434 222*4882a593Smuzhiyun #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434) 223*4882a593Smuzhiyun #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c 224*4882a593Smuzhiyun #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c) 225*4882a593Smuzhiyun #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444 226*4882a593Smuzhiyun #define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444) 227*4882a593Smuzhiyun #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454 228*4882a593Smuzhiyun #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454) 229*4882a593Smuzhiyun #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c 230*4882a593Smuzhiyun #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c) 231*4882a593Smuzhiyun #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464 232*4882a593Smuzhiyun #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) 233*4882a593Smuzhiyun #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 234*4882a593Smuzhiyun #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) 235*4882a593Smuzhiyun #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c 236*4882a593Smuzhiyun #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) 237*4882a593Smuzhiyun #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 238*4882a593Smuzhiyun #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) 239*4882a593Smuzhiyun #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 240*4882a593Smuzhiyun #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624) 241*4882a593Smuzhiyun #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c 242*4882a593Smuzhiyun #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c) 243*4882a593Smuzhiyun #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 244*4882a593Smuzhiyun #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634) 245*4882a593Smuzhiyun #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 246*4882a593Smuzhiyun #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c) 247*4882a593Smuzhiyun #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724 248*4882a593Smuzhiyun #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724) 249*4882a593Smuzhiyun #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 250*4882a593Smuzhiyun #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c) 251*4882a593Smuzhiyun #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744 252*4882a593Smuzhiyun #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744) 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun /* PRM.IVAHD_PRM register offsets */ 255*4882a593Smuzhiyun #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000 256*4882a593Smuzhiyun #define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000) 257*4882a593Smuzhiyun #define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004 258*4882a593Smuzhiyun #define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004) 259*4882a593Smuzhiyun #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010 260*4882a593Smuzhiyun #define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010) 261*4882a593Smuzhiyun #define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014 262*4882a593Smuzhiyun #define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014) 263*4882a593Smuzhiyun #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024 264*4882a593Smuzhiyun #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024) 265*4882a593Smuzhiyun #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c 266*4882a593Smuzhiyun #define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c) 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun /* PRM.CAM_PRM register offsets */ 269*4882a593Smuzhiyun #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000 270*4882a593Smuzhiyun #define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000) 271*4882a593Smuzhiyun #define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004 272*4882a593Smuzhiyun #define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004) 273*4882a593Smuzhiyun #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 274*4882a593Smuzhiyun #define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024) 275*4882a593Smuzhiyun #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c 276*4882a593Smuzhiyun #define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c) 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun /* PRM.DSS_PRM register offsets */ 279*4882a593Smuzhiyun #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000 280*4882a593Smuzhiyun #define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000) 281*4882a593Smuzhiyun #define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004 282*4882a593Smuzhiyun #define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004) 283*4882a593Smuzhiyun #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020 284*4882a593Smuzhiyun #define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020) 285*4882a593Smuzhiyun #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 286*4882a593Smuzhiyun #define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024) 287*4882a593Smuzhiyun #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c 288*4882a593Smuzhiyun #define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c) 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun /* PRM.GFX_PRM register offsets */ 291*4882a593Smuzhiyun #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000 292*4882a593Smuzhiyun #define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000) 293*4882a593Smuzhiyun #define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004 294*4882a593Smuzhiyun #define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004) 295*4882a593Smuzhiyun #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024 296*4882a593Smuzhiyun #define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024) 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun /* PRM.L3INIT_PRM register offsets */ 299*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 300*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000) 301*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004 302*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004) 303*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 304*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028) 305*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 306*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c) 307*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 308*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030) 309*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 310*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034) 311*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 312*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038) 313*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c 314*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c) 315*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040 316*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040) 317*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044 318*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044) 319*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058 320*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058) 321*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c 322*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c) 323*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060 324*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060) 325*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064 326*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064) 327*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068 328*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068) 329*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c 330*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c) 331*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c 332*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c) 333*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084 334*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084) 335*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 336*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088) 337*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 338*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c) 339*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094 340*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094) 341*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098 342*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098) 343*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c 344*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c) 345*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac 346*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac) 347*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0 348*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0) 349*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4 350*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4) 351*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8 352*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8) 353*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc 354*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc) 355*4882a593Smuzhiyun #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0 356*4882a593Smuzhiyun #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0) 357*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4 358*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4) 359*4882a593Smuzhiyun #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4 360*4882a593Smuzhiyun #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4) 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun /* PRM.L4PER_PRM register offsets */ 363*4882a593Smuzhiyun #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 364*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000) 365*4882a593Smuzhiyun #define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004 366*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004) 367*4882a593Smuzhiyun #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024 368*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024) 369*4882a593Smuzhiyun #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028 370*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028) 371*4882a593Smuzhiyun #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c 372*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c) 373*4882a593Smuzhiyun #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030 374*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030) 375*4882a593Smuzhiyun #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034 376*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034) 377*4882a593Smuzhiyun #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038 378*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038) 379*4882a593Smuzhiyun #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c 380*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c) 381*4882a593Smuzhiyun #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040 382*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040) 383*4882a593Smuzhiyun #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044 384*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044) 385*4882a593Smuzhiyun #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048 386*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048) 387*4882a593Smuzhiyun #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c 388*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c) 389*4882a593Smuzhiyun #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050 390*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050) 391*4882a593Smuzhiyun #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054 392*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054) 393*4882a593Smuzhiyun #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c 394*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c) 395*4882a593Smuzhiyun #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 396*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060) 397*4882a593Smuzhiyun #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 398*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064) 399*4882a593Smuzhiyun #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 400*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068) 401*4882a593Smuzhiyun #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c 402*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c) 403*4882a593Smuzhiyun #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 404*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070) 405*4882a593Smuzhiyun #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 406*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074) 407*4882a593Smuzhiyun #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 408*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078) 409*4882a593Smuzhiyun #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c 410*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c) 411*4882a593Smuzhiyun #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 412*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080) 413*4882a593Smuzhiyun #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 414*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084) 415*4882a593Smuzhiyun #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c 416*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c) 417*4882a593Smuzhiyun #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090 418*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090) 419*4882a593Smuzhiyun #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094 420*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094) 421*4882a593Smuzhiyun #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098 422*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098) 423*4882a593Smuzhiyun #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c 424*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c) 425*4882a593Smuzhiyun #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 426*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0) 427*4882a593Smuzhiyun #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 428*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4) 429*4882a593Smuzhiyun #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 430*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8) 431*4882a593Smuzhiyun #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac 432*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac) 433*4882a593Smuzhiyun #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 434*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0) 435*4882a593Smuzhiyun #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 436*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4) 437*4882a593Smuzhiyun #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 438*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8) 439*4882a593Smuzhiyun #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc 440*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc) 441*4882a593Smuzhiyun #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0 442*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0) 443*4882a593Smuzhiyun #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0 444*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0) 445*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4 446*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4) 447*4882a593Smuzhiyun #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8 448*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8) 449*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc 450*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc) 451*4882a593Smuzhiyun #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0 452*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0) 453*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4 454*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4) 455*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec 456*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec) 457*4882a593Smuzhiyun #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 458*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0) 459*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 460*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4) 461*4882a593Smuzhiyun #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 462*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8) 463*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc 464*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc) 465*4882a593Smuzhiyun #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 466*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100) 467*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 468*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104) 469*4882a593Smuzhiyun #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 470*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108) 471*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c 472*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c) 473*4882a593Smuzhiyun #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120 474*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120) 475*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124 476*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124) 477*4882a593Smuzhiyun #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128 478*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128) 479*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c 480*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c) 481*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134 482*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134) 483*4882a593Smuzhiyun #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138 484*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138) 485*4882a593Smuzhiyun #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c 486*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c) 487*4882a593Smuzhiyun #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 488*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140) 489*4882a593Smuzhiyun #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 490*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144) 491*4882a593Smuzhiyun #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 492*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148) 493*4882a593Smuzhiyun #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c 494*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c) 495*4882a593Smuzhiyun #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 496*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150) 497*4882a593Smuzhiyun #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 498*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154) 499*4882a593Smuzhiyun #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 500*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158) 501*4882a593Smuzhiyun #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c 502*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c) 503*4882a593Smuzhiyun #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160 504*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160) 505*4882a593Smuzhiyun #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164 506*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164) 507*4882a593Smuzhiyun #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168 508*4882a593Smuzhiyun #define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168) 509*4882a593Smuzhiyun #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c 510*4882a593Smuzhiyun #define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c) 511*4882a593Smuzhiyun #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 512*4882a593Smuzhiyun #define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4) 513*4882a593Smuzhiyun #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac 514*4882a593Smuzhiyun #define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac) 515*4882a593Smuzhiyun #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 516*4882a593Smuzhiyun #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4) 517*4882a593Smuzhiyun #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc 518*4882a593Smuzhiyun #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc) 519*4882a593Smuzhiyun #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 520*4882a593Smuzhiyun #define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4) 521*4882a593Smuzhiyun #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc 522*4882a593Smuzhiyun #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc) 523*4882a593Smuzhiyun #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc 524*4882a593Smuzhiyun #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc) 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun /* PRM.CEFUSE_PRM register offsets */ 527*4882a593Smuzhiyun #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 528*4882a593Smuzhiyun #define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000) 529*4882a593Smuzhiyun #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004 530*4882a593Smuzhiyun #define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004) 531*4882a593Smuzhiyun #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024 532*4882a593Smuzhiyun #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024) 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun /* PRM.WKUP_PRM register offsets */ 535*4882a593Smuzhiyun #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024 536*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024) 537*4882a593Smuzhiyun #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c 538*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c) 539*4882a593Smuzhiyun #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030 540*4882a593Smuzhiyun #define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030) 541*4882a593Smuzhiyun #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034 542*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034) 543*4882a593Smuzhiyun #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038 544*4882a593Smuzhiyun #define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038) 545*4882a593Smuzhiyun #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c 546*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c) 547*4882a593Smuzhiyun #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040 548*4882a593Smuzhiyun #define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040) 549*4882a593Smuzhiyun #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044 550*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044) 551*4882a593Smuzhiyun #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048 552*4882a593Smuzhiyun #define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048) 553*4882a593Smuzhiyun #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c 554*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c) 555*4882a593Smuzhiyun #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054 556*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054) 557*4882a593Smuzhiyun #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058 558*4882a593Smuzhiyun #define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058) 559*4882a593Smuzhiyun #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c 560*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c) 561*4882a593Smuzhiyun #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064 562*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064) 563*4882a593Smuzhiyun #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078 564*4882a593Smuzhiyun #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078) 565*4882a593Smuzhiyun #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c 566*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c) 567*4882a593Smuzhiyun #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080 568*4882a593Smuzhiyun #define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080) 569*4882a593Smuzhiyun #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084 570*4882a593Smuzhiyun #define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084) 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun /* PRM.WKUP_CM register offsets */ 573*4882a593Smuzhiyun #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 574*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000) 575*4882a593Smuzhiyun #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020 576*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020) 577*4882a593Smuzhiyun #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028 578*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028) 579*4882a593Smuzhiyun #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030 580*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030) 581*4882a593Smuzhiyun #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038 582*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038) 583*4882a593Smuzhiyun #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040 584*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040) 585*4882a593Smuzhiyun #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048 586*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048) 587*4882a593Smuzhiyun #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050 588*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050) 589*4882a593Smuzhiyun #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058 590*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058) 591*4882a593Smuzhiyun #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060 592*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060) 593*4882a593Smuzhiyun #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078 594*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078) 595*4882a593Smuzhiyun #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080 596*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080) 597*4882a593Smuzhiyun #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088 598*4882a593Smuzhiyun #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088) 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun /* PRM.EMU_PRM register offsets */ 601*4882a593Smuzhiyun #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000 602*4882a593Smuzhiyun #define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000) 603*4882a593Smuzhiyun #define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004 604*4882a593Smuzhiyun #define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004) 605*4882a593Smuzhiyun #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 606*4882a593Smuzhiyun #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024) 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun /* PRM.EMU_CM register offsets */ 609*4882a593Smuzhiyun #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000 610*4882a593Smuzhiyun #define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000) 611*4882a593Smuzhiyun #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008 612*4882a593Smuzhiyun #define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008) 613*4882a593Smuzhiyun #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 614*4882a593Smuzhiyun #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020) 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun /* PRM.DEVICE_PRM register offsets */ 617*4882a593Smuzhiyun #define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 618*4882a593Smuzhiyun #define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000) 619*4882a593Smuzhiyun #define OMAP4_PRM_RSTST_OFFSET 0x0004 620*4882a593Smuzhiyun #define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004) 621*4882a593Smuzhiyun #define OMAP4_PRM_RSTTIME_OFFSET 0x0008 622*4882a593Smuzhiyun #define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008) 623*4882a593Smuzhiyun #define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c 624*4882a593Smuzhiyun #define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c) 625*4882a593Smuzhiyun #define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 626*4882a593Smuzhiyun #define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010) 627*4882a593Smuzhiyun #define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014 628*4882a593Smuzhiyun #define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014) 629*4882a593Smuzhiyun #define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018 630*4882a593Smuzhiyun #define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018) 631*4882a593Smuzhiyun #define OMAP4_PRM_IO_COUNT_OFFSET 0x001c 632*4882a593Smuzhiyun #define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c) 633*4882a593Smuzhiyun #define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 634*4882a593Smuzhiyun #define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020) 635*4882a593Smuzhiyun #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 636*4882a593Smuzhiyun #define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024) 637*4882a593Smuzhiyun #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 638*4882a593Smuzhiyun #define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028) 639*4882a593Smuzhiyun #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 640*4882a593Smuzhiyun #define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c) 641*4882a593Smuzhiyun #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 642*4882a593Smuzhiyun #define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030) 643*4882a593Smuzhiyun #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 644*4882a593Smuzhiyun #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034) 645*4882a593Smuzhiyun #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 646*4882a593Smuzhiyun #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038) 647*4882a593Smuzhiyun #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c 648*4882a593Smuzhiyun #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c) 649*4882a593Smuzhiyun #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 650*4882a593Smuzhiyun #define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040) 651*4882a593Smuzhiyun #define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 652*4882a593Smuzhiyun #define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044) 653*4882a593Smuzhiyun #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 654*4882a593Smuzhiyun #define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048) 655*4882a593Smuzhiyun #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c 656*4882a593Smuzhiyun #define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c) 657*4882a593Smuzhiyun #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 658*4882a593Smuzhiyun #define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050) 659*4882a593Smuzhiyun #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 660*4882a593Smuzhiyun #define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054) 661*4882a593Smuzhiyun #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 662*4882a593Smuzhiyun #define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058) 663*4882a593Smuzhiyun #define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c 664*4882a593Smuzhiyun #define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c) 665*4882a593Smuzhiyun #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 666*4882a593Smuzhiyun #define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060) 667*4882a593Smuzhiyun #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 668*4882a593Smuzhiyun #define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064) 669*4882a593Smuzhiyun #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 670*4882a593Smuzhiyun #define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068) 671*4882a593Smuzhiyun #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c 672*4882a593Smuzhiyun #define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c) 673*4882a593Smuzhiyun #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 674*4882a593Smuzhiyun #define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070) 675*4882a593Smuzhiyun #define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 676*4882a593Smuzhiyun #define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074) 677*4882a593Smuzhiyun #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 678*4882a593Smuzhiyun #define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078) 679*4882a593Smuzhiyun #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c 680*4882a593Smuzhiyun #define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c) 681*4882a593Smuzhiyun #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 682*4882a593Smuzhiyun #define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080) 683*4882a593Smuzhiyun #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 684*4882a593Smuzhiyun #define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084) 685*4882a593Smuzhiyun #define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 686*4882a593Smuzhiyun #define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088) 687*4882a593Smuzhiyun #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c 688*4882a593Smuzhiyun #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c) 689*4882a593Smuzhiyun #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 690*4882a593Smuzhiyun #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090) 691*4882a593Smuzhiyun #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 692*4882a593Smuzhiyun #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094) 693*4882a593Smuzhiyun #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 694*4882a593Smuzhiyun #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098) 695*4882a593Smuzhiyun #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c 696*4882a593Smuzhiyun #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c) 697*4882a593Smuzhiyun #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 698*4882a593Smuzhiyun #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) 699*4882a593Smuzhiyun #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 700*4882a593Smuzhiyun #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) 701*4882a593Smuzhiyun #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 702*4882a593Smuzhiyun #define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) 703*4882a593Smuzhiyun #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac 704*4882a593Smuzhiyun #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) 705*4882a593Smuzhiyun #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 706*4882a593Smuzhiyun #define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0) 707*4882a593Smuzhiyun #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4 708*4882a593Smuzhiyun #define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4) 709*4882a593Smuzhiyun #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8 710*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8) 711*4882a593Smuzhiyun #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc 712*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc) 713*4882a593Smuzhiyun #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0 714*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0) 715*4882a593Smuzhiyun #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4 716*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4) 717*4882a593Smuzhiyun #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8 718*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8) 719*4882a593Smuzhiyun #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc 720*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc) 721*4882a593Smuzhiyun #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0 722*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0) 723*4882a593Smuzhiyun #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4 724*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4) 725*4882a593Smuzhiyun #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8 726*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8) 727*4882a593Smuzhiyun #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc 728*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc) 729*4882a593Smuzhiyun #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 730*4882a593Smuzhiyun #define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0) 731*4882a593Smuzhiyun #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 732*4882a593Smuzhiyun #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4) 733*4882a593Smuzhiyun #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 734*4882a593Smuzhiyun #define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8) 735*4882a593Smuzhiyun #define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec 736*4882a593Smuzhiyun #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) 737*4882a593Smuzhiyun #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 738*4882a593Smuzhiyun #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) 739*4882a593Smuzhiyun #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 740*4882a593Smuzhiyun #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) 741*4882a593Smuzhiyun #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 742*4882a593Smuzhiyun #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) 743*4882a593Smuzhiyun 744*4882a593Smuzhiyun #endif 745