1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2010 Nokia Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Paul Walmsley 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H 11*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_PRM_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "prcm-common.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun # ifndef __ASSEMBLER__ 16*4882a593Smuzhiyun extern struct omap_domain_base prm_base; 17*4882a593Smuzhiyun extern u16 prm_features; 18*4882a593Smuzhiyun extern void omap2_set_globals_prm(void __iomem *prm); 19*4882a593Smuzhiyun int omap_prcm_init(void); 20*4882a593Smuzhiyun int omap2_prm_base_init(void); 21*4882a593Smuzhiyun int omap2_prcm_base_init(void); 22*4882a593Smuzhiyun # endif 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * prm_features flag values 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * PRM_HAS_IO_WAKEUP: has IO wakeup capability 28*4882a593Smuzhiyun * PRM_HAS_VOLTAGE: has voltage domains 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define PRM_HAS_IO_WAKEUP BIT(0) 31*4882a593Smuzhiyun #define PRM_HAS_VOLTAGE BIT(1) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP 35*4882a593Smuzhiyun * module to softreset 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define MAX_MODULE_SOFTRESET_WAIT 10000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP 41*4882a593Smuzhiyun * submodule to exit hardreset 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun #define MAX_MODULE_HARDRESET_WAIT 10000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * Register bitfields 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP 51*4882a593Smuzhiyun * 52*4882a593Smuzhiyun * 2430: PM_PWSTST_MDM 53*4882a593Smuzhiyun * 54*4882a593Smuzhiyun * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, 55*4882a593Smuzhiyun * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, 56*4882a593Smuzhiyun * PM_PWSTST_NEON 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define OMAP_INTRANSITION_MASK (1 << 20) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP 63*4882a593Smuzhiyun * 64*4882a593Smuzhiyun * 2430: PM_PWSTST_MDM 65*4882a593Smuzhiyun * 66*4882a593Smuzhiyun * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, 67*4882a593Smuzhiyun * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, 68*4882a593Smuzhiyun * PM_PWSTST_NEON 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun #define OMAP_POWERSTATEST_SHIFT 0 71*4882a593Smuzhiyun #define OMAP_POWERSTATEST_MASK (0x3 << 0) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 75*4882a593Smuzhiyun * PM_PWSTCTRL_DSP, PM_PWSTST_MPU 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * 2430: PM_PWSTCTRL_MDM shared bits 78*4882a593Smuzhiyun * 79*4882a593Smuzhiyun * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, 80*4882a593Smuzhiyun * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, 81*4882a593Smuzhiyun * PM_PWSTCTRL_NEON shared bits 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun #define OMAP_POWERSTATE_SHIFT 0 84*4882a593Smuzhiyun #define OMAP_POWERSTATE_MASK (0x3 << 0) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* 87*4882a593Smuzhiyun * Standardized OMAP reset source bits 88*4882a593Smuzhiyun * 89*4882a593Smuzhiyun * To the extent these happen to match the hardware register bit 90*4882a593Smuzhiyun * shifts, it's purely coincidental. Used by omap-wdt.c. 91*4882a593Smuzhiyun * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever 92*4882a593Smuzhiyun * there are any bits remaining in the global PRM_RSTST register that 93*4882a593Smuzhiyun * haven't been identified, or when the PRM code for the current SoC 94*4882a593Smuzhiyun * doesn't know how to interpret the register. 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun #define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0 97*4882a593Smuzhiyun #define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1 98*4882a593Smuzhiyun #define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2 99*4882a593Smuzhiyun #define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3 100*4882a593Smuzhiyun #define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4 101*4882a593Smuzhiyun #define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5 102*4882a593Smuzhiyun #define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6 103*4882a593Smuzhiyun #define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7 104*4882a593Smuzhiyun #define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8 105*4882a593Smuzhiyun #define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9 106*4882a593Smuzhiyun #define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10 107*4882a593Smuzhiyun #define OMAP_C2C_RST_SRC_ID_SHIFT 11 108*4882a593Smuzhiyun #define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #ifndef __ASSEMBLER__ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /** 113*4882a593Smuzhiyun * struct prm_reset_src_map - map register bitshifts to standard bitshifts 114*4882a593Smuzhiyun * @reg_shift: bitshift in the PRM reset source register 115*4882a593Smuzhiyun * @std_shift: bitshift equivalent in the standard reset source list 116*4882a593Smuzhiyun * 117*4882a593Smuzhiyun * The fields are signed because -1 is used as a terminator. 118*4882a593Smuzhiyun */ 119*4882a593Smuzhiyun struct prm_reset_src_map { 120*4882a593Smuzhiyun s8 reg_shift; 121*4882a593Smuzhiyun s8 std_shift; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /** 125*4882a593Smuzhiyun * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations 126*4882a593Smuzhiyun * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl 127*4882a593Smuzhiyun * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn 128*4882a593Smuzhiyun * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn 129*4882a593Smuzhiyun * @late_init: ptr to the late init function 130*4882a593Smuzhiyun * @assert_hardreset: ptr to the SoC PRM hardreset assert impl 131*4882a593Smuzhiyun * @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl 132*4882a593Smuzhiyun * 133*4882a593Smuzhiyun * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are 134*4882a593Smuzhiyun * deprecated. 135*4882a593Smuzhiyun */ 136*4882a593Smuzhiyun struct prm_ll_data { 137*4882a593Smuzhiyun u32 (*read_reset_sources)(void); 138*4882a593Smuzhiyun bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx); 139*4882a593Smuzhiyun void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx); 140*4882a593Smuzhiyun int (*late_init)(void); 141*4882a593Smuzhiyun int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset); 142*4882a593Smuzhiyun int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod, 143*4882a593Smuzhiyun u16 offset, u16 st_offset); 144*4882a593Smuzhiyun int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod, 145*4882a593Smuzhiyun u16 offset); 146*4882a593Smuzhiyun void (*reset_system)(void); 147*4882a593Smuzhiyun int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask); 148*4882a593Smuzhiyun u32 (*vp_check_txdone)(u8 vp_id); 149*4882a593Smuzhiyun void (*vp_clear_txdone)(u8 vp_id); 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun extern int prm_register(struct prm_ll_data *pld); 153*4882a593Smuzhiyun extern int prm_unregister(struct prm_ll_data *pld); 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset); 156*4882a593Smuzhiyun int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod, 157*4882a593Smuzhiyun u16 offset, u16 st_offset); 158*4882a593Smuzhiyun int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset); 159*4882a593Smuzhiyun extern u32 prm_read_reset_sources(void); 160*4882a593Smuzhiyun extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx); 161*4882a593Smuzhiyun extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx); 162*4882a593Smuzhiyun void omap_prm_reset_system(void); 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun void omap_prm_reconfigure_io_chain(void); 165*4882a593Smuzhiyun int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask); 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* 168*4882a593Smuzhiyun * Voltage Processor (VP) identifiers 169*4882a593Smuzhiyun */ 170*4882a593Smuzhiyun #define OMAP3_VP_VDD_MPU_ID 0 171*4882a593Smuzhiyun #define OMAP3_VP_VDD_CORE_ID 1 172*4882a593Smuzhiyun #define OMAP4_VP_VDD_CORE_ID 0 173*4882a593Smuzhiyun #define OMAP4_VP_VDD_IVA_ID 1 174*4882a593Smuzhiyun #define OMAP4_VP_VDD_MPU_ID 2 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun u32 omap_prm_vp_check_txdone(u8 vp_id); 177*4882a593Smuzhiyun void omap_prm_vp_clear_txdone(u8 vp_id); 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #endif 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #endif 183