1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP44xx Power Management register bits 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009-2010 Texas Instruments, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2009-2010 Nokia Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Paul Walmsley (paul@pwsan.com) 9*4882a593Smuzhiyun * Rajendra Nayak (rnayak@ti.com) 10*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 13*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 14*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 15*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 16*4882a593Smuzhiyun * up-to-date with the file contents. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 20*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define OMAP4430_C2C_RST_SHIFT 10 23*4882a593Smuzhiyun #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) 24*4882a593Smuzhiyun #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) 25*4882a593Smuzhiyun #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) 26*4882a593Smuzhiyun #define OMAP4430_DATA_SHIFT 16 27*4882a593Smuzhiyun #define OMAP4430_ERRORGAIN_MASK (0xff << 16) 28*4882a593Smuzhiyun #define OMAP4430_ERROROFFSET_MASK (0xff << 24) 29*4882a593Smuzhiyun #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 30*4882a593Smuzhiyun #define OMAP4430_FORCEUPDATE_MASK (1 << 1) 31*4882a593Smuzhiyun #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 32*4882a593Smuzhiyun #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 33*4882a593Smuzhiyun #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) 34*4882a593Smuzhiyun #define OMAP4430_HSMCODE_MASK (0x7 << 0) 35*4882a593Smuzhiyun #define OMAP4430_SRMODEEN_MASK (1 << 4) 36*4882a593Smuzhiyun #define OMAP4430_HSMODEEN_MASK (1 << 3) 37*4882a593Smuzhiyun #define OMAP4430_HSSCLL_SHIFT 24 38*4882a593Smuzhiyun #define OMAP4430_ICEPICK_RST_SHIFT 9 39*4882a593Smuzhiyun #define OMAP4430_INITVDD_MASK (1 << 2) 40*4882a593Smuzhiyun #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) 41*4882a593Smuzhiyun #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 42*4882a593Smuzhiyun #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 43*4882a593Smuzhiyun #define OMAP4430_LOGICRETSTATE_SHIFT 2 44*4882a593Smuzhiyun #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) 45*4882a593Smuzhiyun #define OMAP4430_LOGICSTATEST_SHIFT 2 46*4882a593Smuzhiyun #define OMAP4430_LOGICSTATEST_MASK (1 << 2) 47*4882a593Smuzhiyun #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) 48*4882a593Smuzhiyun #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) 49*4882a593Smuzhiyun #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 50*4882a593Smuzhiyun #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) 51*4882a593Smuzhiyun #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 52*4882a593Smuzhiyun #define OMAP4430_MPU_WDT_RST_SHIFT 3 53*4882a593Smuzhiyun #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) 54*4882a593Smuzhiyun #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) 55*4882a593Smuzhiyun #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) 56*4882a593Smuzhiyun #define OMAP4430_OFF_SHIFT 0 57*4882a593Smuzhiyun #define OMAP4430_ON_SHIFT 24 58*4882a593Smuzhiyun #define OMAP4430_ON_MASK (0xff << 24) 59*4882a593Smuzhiyun #define OMAP4430_ONLP_SHIFT 16 60*4882a593Smuzhiyun #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 61*4882a593Smuzhiyun #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 62*4882a593Smuzhiyun #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 63*4882a593Smuzhiyun #define OMAP4430_REGADDR_SHIFT 8 64*4882a593Smuzhiyun #define OMAP4430_RET_SHIFT 8 65*4882a593Smuzhiyun #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) 66*4882a593Smuzhiyun #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 67*4882a593Smuzhiyun #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) 68*4882a593Smuzhiyun #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 69*4882a593Smuzhiyun #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) 70*4882a593Smuzhiyun #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 71*4882a593Smuzhiyun #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) 72*4882a593Smuzhiyun #define OMAP4430_SCLH_SHIFT 0 73*4882a593Smuzhiyun #define OMAP4430_SCLL_SHIFT 8 74*4882a593Smuzhiyun #define OMAP4430_SECURE_WDT_RST_SHIFT 4 75*4882a593Smuzhiyun #define OMAP4430_SLAVEADDR_SHIFT 0 76*4882a593Smuzhiyun #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 77*4882a593Smuzhiyun #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 78*4882a593Smuzhiyun #define OMAP4430_TIMEOUT_SHIFT 0 79*4882a593Smuzhiyun #define OMAP4430_TIMEOUTEN_MASK (1 << 3) 80*4882a593Smuzhiyun #define OMAP4430_VALID_MASK (1 << 24) 81*4882a593Smuzhiyun #define OMAP4430_VDDMAX_SHIFT 24 82*4882a593Smuzhiyun #define OMAP4430_VDDMIN_SHIFT 16 83*4882a593Smuzhiyun #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 84*4882a593Smuzhiyun #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 85*4882a593Smuzhiyun #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 86*4882a593Smuzhiyun #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) 87*4882a593Smuzhiyun #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) 88*4882a593Smuzhiyun #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) 89*4882a593Smuzhiyun #define OMAP4430_VPENABLE_MASK (1 << 0) 90*4882a593Smuzhiyun #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) 91*4882a593Smuzhiyun #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) 92*4882a593Smuzhiyun #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) 93*4882a593Smuzhiyun #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) 94*4882a593Smuzhiyun #define OMAP4430_VSTEPMAX_SHIFT 0 95*4882a593Smuzhiyun #define OMAP4430_VSTEPMIN_SHIFT 0 96*4882a593Smuzhiyun #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) 97*4882a593Smuzhiyun #define OMAP4430_WUCLK_STATUS_SHIFT 9 98*4882a593Smuzhiyun #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) 99*4882a593Smuzhiyun #endif 100