1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * AM33XX PRM_XXX register bits 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 7*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 8*4882a593Smuzhiyun * published by the Free Software Foundation version 2. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty 12*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*4882a593Smuzhiyun * GNU General Public License for more details. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H 17*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include "prm.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) 22*4882a593Smuzhiyun #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) 23*4882a593Smuzhiyun #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) 24*4882a593Smuzhiyun #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) 25*4882a593Smuzhiyun #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) 26*4882a593Smuzhiyun #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) 27*4882a593Smuzhiyun #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) 28*4882a593Smuzhiyun #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) 29*4882a593Smuzhiyun #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 30*4882a593Smuzhiyun #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 31*4882a593Smuzhiyun #define AM33XX_LOGICRETSTATE_MASK (1 << 2) 32*4882a593Smuzhiyun #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) 33*4882a593Smuzhiyun #define AM33XX_LOGICSTATEST_SHIFT 2 34*4882a593Smuzhiyun #define AM33XX_LOGICSTATEST_MASK (1 << 2) 35*4882a593Smuzhiyun #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 36*4882a593Smuzhiyun #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) 37*4882a593Smuzhiyun #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) 38*4882a593Smuzhiyun #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) 39*4882a593Smuzhiyun #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) 40*4882a593Smuzhiyun #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) 41*4882a593Smuzhiyun #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) 42*4882a593Smuzhiyun #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) 43*4882a593Smuzhiyun #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) 44*4882a593Smuzhiyun #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) 45*4882a593Smuzhiyun #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) 46*4882a593Smuzhiyun #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) 47*4882a593Smuzhiyun #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) 48*4882a593Smuzhiyun #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) 49*4882a593Smuzhiyun #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) 50*4882a593Smuzhiyun #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) 51*4882a593Smuzhiyun #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) 52*4882a593Smuzhiyun #endif 53