1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP54xx PRCM MPU instance offset macros 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Paul Walmsley (paul@pwsan.com) 8*4882a593Smuzhiyun * Rajendra Nayak (rnayak@ti.com) 9*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 12*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 13*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 14*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 15*4882a593Smuzhiyun * up-to-date with the file contents. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H 19*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include "prcm_mpu_44xx_54xx.h" 22*4882a593Smuzhiyun #include "common.h" 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_BASE 0x48243000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \ 27*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg)) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* PRCM_MPU instances */ 30*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000 31*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200 32*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400 33*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600 34*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800 35*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* PRCM_MPU clockdomain register offsets (from instance start) */ 38*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000 39*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * PRCM_MPU 44*4882a593Smuzhiyun * 45*4882a593Smuzhiyun * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) 46*4882a593Smuzhiyun * point of view the PRCM_MPU is a single entity. It shares the same 47*4882a593Smuzhiyun * programming model as the global PRCM and thus can be assimilate as two new 48*4882a593Smuzhiyun * MOD inside the PRCM 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */ 52*4882a593Smuzhiyun #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* PRCM_MPU.PRCM_MPU_DEVICE register offsets */ 55*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 56*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 57*4882a593Smuzhiyun #define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010 58*4882a593Smuzhiyun #define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */ 61*4882a593Smuzhiyun #define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 62*4882a593Smuzhiyun #define OMAP54XX_PM_CPU0_PWRSTST_OFFSET 0x0004 63*4882a593Smuzhiyun #define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010 64*4882a593Smuzhiyun #define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014 65*4882a593Smuzhiyun #define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */ 68*4882a593Smuzhiyun #define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000 69*4882a593Smuzhiyun #define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020 70*4882a593Smuzhiyun #define OMAP54XX_CM_CPU0_CPU0_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */ 73*4882a593Smuzhiyun #define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 74*4882a593Smuzhiyun #define OMAP54XX_PM_CPU1_PWRSTST_OFFSET 0x0004 75*4882a593Smuzhiyun #define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010 76*4882a593Smuzhiyun #define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014 77*4882a593Smuzhiyun #define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */ 80*4882a593Smuzhiyun #define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000 81*4882a593Smuzhiyun #define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020 82*4882a593Smuzhiyun #define OMAP54XX_CM_CPU1_CPU1_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif 85