1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP44xx PRCM MPU instance offset macros 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010, 2012 Texas Instruments, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2010 Nokia Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Paul Walmsley (paul@pwsan.com) 9*4882a593Smuzhiyun * Rajendra Nayak (rnayak@ti.com) 10*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 13*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 14*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 15*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 16*4882a593Smuzhiyun * up-to-date with the file contents. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 19*4882a593Smuzhiyun * or "OMAP4430". 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 23*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #include "prcm_mpu_44xx_54xx.h" 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define OMAP4430_PRCM_MPU_BASE 0x48243000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ 30*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* PRCM_MPU instances */ 33*4882a593Smuzhiyun #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000 34*4882a593Smuzhiyun #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200 35*4882a593Smuzhiyun #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 36*4882a593Smuzhiyun #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* PRCM_MPU clockdomain register offsets (from instance start) */ 39*4882a593Smuzhiyun #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018 40*4882a593Smuzhiyun #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * PRCM_MPU 45*4882a593Smuzhiyun * 46*4882a593Smuzhiyun * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) 47*4882a593Smuzhiyun * point of view the PRCM_MPU is a single entity. It shares the same 48*4882a593Smuzhiyun * programming model as the global PRCM and thus can be assimilate as two new 49*4882a593Smuzhiyun * MOD inside the PRCM 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ 53*4882a593Smuzhiyun #define OMAP4_REVISION_PRCM_OFFSET 0x0000 54*4882a593Smuzhiyun #define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* PRCM_MPU.DEVICE_PRM register offsets */ 57*4882a593Smuzhiyun #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 58*4882a593Smuzhiyun #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000) 59*4882a593Smuzhiyun #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 60*4882a593Smuzhiyun #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* PRCM_MPU.CPU0 register offsets */ 63*4882a593Smuzhiyun #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 64*4882a593Smuzhiyun #define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000) 65*4882a593Smuzhiyun #define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 66*4882a593Smuzhiyun #define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004) 67*4882a593Smuzhiyun #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 68*4882a593Smuzhiyun #define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008) 69*4882a593Smuzhiyun #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c 70*4882a593Smuzhiyun #define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c) 71*4882a593Smuzhiyun #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 72*4882a593Smuzhiyun #define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010) 73*4882a593Smuzhiyun #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 74*4882a593Smuzhiyun #define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014) 75*4882a593Smuzhiyun #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 76*4882a593Smuzhiyun #define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* PRCM_MPU.CPU1 register offsets */ 79*4882a593Smuzhiyun #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 80*4882a593Smuzhiyun #define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) 81*4882a593Smuzhiyun #define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 82*4882a593Smuzhiyun #define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) 83*4882a593Smuzhiyun #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 84*4882a593Smuzhiyun #define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) 85*4882a593Smuzhiyun #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c 86*4882a593Smuzhiyun #define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) 87*4882a593Smuzhiyun #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 88*4882a593Smuzhiyun #define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) 89*4882a593Smuzhiyun #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 90*4882a593Smuzhiyun #define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) 91*4882a593Smuzhiyun #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 92*4882a593Smuzhiyun #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif 95