1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * AM43x PRCM defines 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License 7*4882a593Smuzhiyun * version 2. This program is licensed "as is" without any warranty of any 8*4882a593Smuzhiyun * kind, whether express or implied. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H 12*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define AM43XX_PRM_PARTITION 1 15*4882a593Smuzhiyun #define AM43XX_CM_PARTITION 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* PRM instances */ 18*4882a593Smuzhiyun #define AM43XX_PRM_OCP_SOCKET_INST 0x0000 19*4882a593Smuzhiyun #define AM43XX_PRM_MPU_INST 0x0300 20*4882a593Smuzhiyun #define AM43XX_PRM_GFX_INST 0x0400 21*4882a593Smuzhiyun #define AM43XX_PRM_RTC_INST 0x0500 22*4882a593Smuzhiyun #define AM43XX_PRM_TAMPER_INST 0x0600 23*4882a593Smuzhiyun #define AM43XX_PRM_CEFUSE_INST 0x0700 24*4882a593Smuzhiyun #define AM43XX_PRM_PER_INST 0x0800 25*4882a593Smuzhiyun #define AM43XX_PRM_WKUP_INST 0x2000 26*4882a593Smuzhiyun #define AM43XX_PRM_DEVICE_INST 0x4000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* PRM_IRQ offsets */ 29*4882a593Smuzhiyun #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 30*4882a593Smuzhiyun #define AM43XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Other PRM offsets */ 33*4882a593Smuzhiyun #define AM43XX_PRM_IO_PMCTRL_OFFSET 0x0024 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* RM RSTCTRL offsets */ 36*4882a593Smuzhiyun #define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 37*4882a593Smuzhiyun #define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 38*4882a593Smuzhiyun #define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* RM RSTST offsets */ 41*4882a593Smuzhiyun #define AM43XX_RM_GFX_RSTST_OFFSET 0x0014 42*4882a593Smuzhiyun #define AM43XX_RM_PER_RSTST_OFFSET 0x0014 43*4882a593Smuzhiyun #define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* CM instances */ 46*4882a593Smuzhiyun #define AM43XX_CM_WKUP_INST 0x2800 47*4882a593Smuzhiyun #define AM43XX_CM_DEVICE_INST 0x4100 48*4882a593Smuzhiyun #define AM43XX_CM_DPLL_INST 0x4200 49*4882a593Smuzhiyun #define AM43XX_CM_MPU_INST 0x8300 50*4882a593Smuzhiyun #define AM43XX_CM_GFX_INST 0x8400 51*4882a593Smuzhiyun #define AM43XX_CM_RTC_INST 0x8500 52*4882a593Smuzhiyun #define AM43XX_CM_TAMPER_INST 0x8600 53*4882a593Smuzhiyun #define AM43XX_CM_CEFUSE_INST 0x8700 54*4882a593Smuzhiyun #define AM43XX_CM_PER_INST 0x8800 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* CD offsets */ 57*4882a593Smuzhiyun #define AM43XX_CM_WKUP_L3_AON_CDOFFS 0x0000 58*4882a593Smuzhiyun #define AM43XX_CM_WKUP_L3S_TSC_CDOFFS 0x0100 59*4882a593Smuzhiyun #define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS 0x0200 60*4882a593Smuzhiyun #define AM43XX_CM_WKUP_WKUP_CDOFFS 0x0300 61*4882a593Smuzhiyun #define AM43XX_CM_MPU_MPU_CDOFFS 0x0000 62*4882a593Smuzhiyun #define AM43XX_CM_GFX_GFX_L3_CDOFFS 0x0000 63*4882a593Smuzhiyun #define AM43XX_CM_RTC_RTC_CDOFFS 0x0000 64*4882a593Smuzhiyun #define AM43XX_CM_TAMPER_TAMPER_CDOFFS 0x0000 65*4882a593Smuzhiyun #define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS 0x0000 66*4882a593Smuzhiyun #define AM43XX_CM_PER_L3_CDOFFS 0x0000 67*4882a593Smuzhiyun #define AM43XX_CM_PER_L3S_CDOFFS 0x0200 68*4882a593Smuzhiyun #define AM43XX_CM_PER_ICSS_CDOFFS 0x0300 69*4882a593Smuzhiyun #define AM43XX_CM_PER_L4LS_CDOFFS 0x0400 70*4882a593Smuzhiyun #define AM43XX_CM_PER_EMIF_CDOFFS 0x0700 71*4882a593Smuzhiyun #define AM43XX_CM_PER_LCDC_CDOFFS 0x0800 72*4882a593Smuzhiyun #define AM43XX_CM_PER_DSS_CDOFFS 0x0a00 73*4882a593Smuzhiyun #define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00 74*4882a593Smuzhiyun #define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* CLK CTRL offsets */ 77*4882a593Smuzhiyun #define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580 78*4882a593Smuzhiyun #define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588 79*4882a593Smuzhiyun #define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590 80*4882a593Smuzhiyun #define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598 81*4882a593Smuzhiyun #define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0 82*4882a593Smuzhiyun #define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428 83*4882a593Smuzhiyun #define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430 84*4882a593Smuzhiyun #define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468 85*4882a593Smuzhiyun #define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438 86*4882a593Smuzhiyun #define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440 87*4882a593Smuzhiyun #define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448 88*4882a593Smuzhiyun #define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478 89*4882a593Smuzhiyun #define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480 90*4882a593Smuzhiyun #define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488 91*4882a593Smuzhiyun #define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8 92*4882a593Smuzhiyun #define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0 93*4882a593Smuzhiyun #define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8 94*4882a593Smuzhiyun #define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0 95*4882a593Smuzhiyun #define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8 96*4882a593Smuzhiyun #define AM43XX_CM_PER_RNG_CLKCTRL_OFFSET 0x04e0 97*4882a593Smuzhiyun #define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500 98*4882a593Smuzhiyun #define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508 99*4882a593Smuzhiyun #define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528 100*4882a593Smuzhiyun #define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530 101*4882a593Smuzhiyun #define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538 102*4882a593Smuzhiyun #define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540 103*4882a593Smuzhiyun #define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548 104*4882a593Smuzhiyun #define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550 105*4882a593Smuzhiyun #define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558 106*4882a593Smuzhiyun #define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228 107*4882a593Smuzhiyun #define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360 108*4882a593Smuzhiyun #define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350 109*4882a593Smuzhiyun #define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358 110*4882a593Smuzhiyun #define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348 111*4882a593Smuzhiyun #define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328 112*4882a593Smuzhiyun #define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340 113*4882a593Smuzhiyun #define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368 114*4882a593Smuzhiyun #define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120 115*4882a593Smuzhiyun #define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338 116*4882a593Smuzhiyun #define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220 117*4882a593Smuzhiyun #define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020 118*4882a593Smuzhiyun #define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248 119*4882a593Smuzhiyun #define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET 0x0258 120*4882a593Smuzhiyun #define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220 121*4882a593Smuzhiyun #define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238 122*4882a593Smuzhiyun #define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240 123*4882a593Smuzhiyun #define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420 124*4882a593Smuzhiyun #define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020 125*4882a593Smuzhiyun #define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078 126*4882a593Smuzhiyun #define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080 127*4882a593Smuzhiyun #define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088 128*4882a593Smuzhiyun #define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090 129*4882a593Smuzhiyun #define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20 130*4882a593Smuzhiyun #define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320 131*4882a593Smuzhiyun #define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 132*4882a593Smuzhiyun #define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0 133*4882a593Smuzhiyun #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 134*4882a593Smuzhiyun #define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040 135*4882a593Smuzhiyun #define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050 136*4882a593Smuzhiyun #define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058 137*4882a593Smuzhiyun #define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028 138*4882a593Smuzhiyun #define AM43XX_CM_PER_DES_CLKCTRL_OFFSET 0x0030 139*4882a593Smuzhiyun #define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560 140*4882a593Smuzhiyun #define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568 141*4882a593Smuzhiyun #define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570 142*4882a593Smuzhiyun #define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578 143*4882a593Smuzhiyun #define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230 144*4882a593Smuzhiyun #define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450 145*4882a593Smuzhiyun #define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458 146*4882a593Smuzhiyun #define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460 147*4882a593Smuzhiyun #define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510 148*4882a593Smuzhiyun #define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518 149*4882a593Smuzhiyun #define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520 150*4882a593Smuzhiyun #define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490 151*4882a593Smuzhiyun #define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498 152*4882a593Smuzhiyun #define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET 0x0260 153*4882a593Smuzhiyun #define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 154*4882a593Smuzhiyun #define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 155*4882a593Smuzhiyun #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 156*4882a593Smuzhiyun #define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 157*4882a593Smuzhiyun #define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0 158*4882a593Smuzhiyun #define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068 159*4882a593Smuzhiyun #define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070 160*4882a593Smuzhiyun #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0720 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #endif 163