1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Common powerdomain framework functions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010-2011 Texas Instruments, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2010 Nokia Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Derived from mach-omap2/powerdomain.c written by Paul Walmsley 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/errno.h> 12*4882a593Smuzhiyun #include <linux/kernel.h> 13*4882a593Smuzhiyun #include <linux/bug.h> 14*4882a593Smuzhiyun #include "pm.h" 15*4882a593Smuzhiyun #include "cm.h" 16*4882a593Smuzhiyun #include "cm-regbits-34xx.h" 17*4882a593Smuzhiyun #include "prm-regbits-34xx.h" 18*4882a593Smuzhiyun #include "prm-regbits-44xx.h" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * OMAP3 and OMAP4 specific register bit initialisations 22*4882a593Smuzhiyun * Notice that the names here are not according to each power 23*4882a593Smuzhiyun * domain but the bit mapping used applies to all of them 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ 26*4882a593Smuzhiyun #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK 27*4882a593Smuzhiyun #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK 28*4882a593Smuzhiyun #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK 29*4882a593Smuzhiyun #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK 30*4882a593Smuzhiyun #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ 33*4882a593Smuzhiyun #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK 34*4882a593Smuzhiyun #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK 35*4882a593Smuzhiyun #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK 36*4882a593Smuzhiyun #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK 37*4882a593Smuzhiyun #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* OMAP3 and OMAP4 Memory Status bits */ 40*4882a593Smuzhiyun #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK 41*4882a593Smuzhiyun #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK 42*4882a593Smuzhiyun #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK 43*4882a593Smuzhiyun #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK 44*4882a593Smuzhiyun #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Common Internal functions used across OMAP rev's*/ omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank)47*4882a593Smuzhiyunu32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank) 48*4882a593Smuzhiyun { 49*4882a593Smuzhiyun switch (bank) { 50*4882a593Smuzhiyun case 0: 51*4882a593Smuzhiyun return OMAP_MEM0_ONSTATE_MASK; 52*4882a593Smuzhiyun case 1: 53*4882a593Smuzhiyun return OMAP_MEM1_ONSTATE_MASK; 54*4882a593Smuzhiyun case 2: 55*4882a593Smuzhiyun return OMAP_MEM2_ONSTATE_MASK; 56*4882a593Smuzhiyun case 3: 57*4882a593Smuzhiyun return OMAP_MEM3_ONSTATE_MASK; 58*4882a593Smuzhiyun case 4: 59*4882a593Smuzhiyun return OMAP_MEM4_ONSTATE_MASK; 60*4882a593Smuzhiyun default: 61*4882a593Smuzhiyun WARN_ON(1); /* should never happen */ 62*4882a593Smuzhiyun return -EEXIST; 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun return 0; 65*4882a593Smuzhiyun } 66*4882a593Smuzhiyun omap2_pwrdm_get_mem_bank_retst_mask(u8 bank)67*4882a593Smuzhiyunu32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank) 68*4882a593Smuzhiyun { 69*4882a593Smuzhiyun switch (bank) { 70*4882a593Smuzhiyun case 0: 71*4882a593Smuzhiyun return OMAP_MEM0_RETSTATE_MASK; 72*4882a593Smuzhiyun case 1: 73*4882a593Smuzhiyun return OMAP_MEM1_RETSTATE_MASK; 74*4882a593Smuzhiyun case 2: 75*4882a593Smuzhiyun return OMAP_MEM2_RETSTATE_MASK; 76*4882a593Smuzhiyun case 3: 77*4882a593Smuzhiyun return OMAP_MEM3_RETSTATE_MASK; 78*4882a593Smuzhiyun case 4: 79*4882a593Smuzhiyun return OMAP_MEM4_RETSTATE_MASK; 80*4882a593Smuzhiyun default: 81*4882a593Smuzhiyun WARN_ON(1); /* should never happen */ 82*4882a593Smuzhiyun return -EEXIST; 83*4882a593Smuzhiyun } 84*4882a593Smuzhiyun return 0; 85*4882a593Smuzhiyun } 86*4882a593Smuzhiyun omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)87*4882a593Smuzhiyunu32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank) 88*4882a593Smuzhiyun { 89*4882a593Smuzhiyun switch (bank) { 90*4882a593Smuzhiyun case 0: 91*4882a593Smuzhiyun return OMAP_MEM0_STATEST_MASK; 92*4882a593Smuzhiyun case 1: 93*4882a593Smuzhiyun return OMAP_MEM1_STATEST_MASK; 94*4882a593Smuzhiyun case 2: 95*4882a593Smuzhiyun return OMAP_MEM2_STATEST_MASK; 96*4882a593Smuzhiyun case 3: 97*4882a593Smuzhiyun return OMAP_MEM3_STATEST_MASK; 98*4882a593Smuzhiyun case 4: 99*4882a593Smuzhiyun return OMAP_MEM4_STATEST_MASK; 100*4882a593Smuzhiyun default: 101*4882a593Smuzhiyun WARN_ON(1); /* should never happen */ 102*4882a593Smuzhiyun return -EEXIST; 103*4882a593Smuzhiyun } 104*4882a593Smuzhiyun return 0; 105*4882a593Smuzhiyun } 106*4882a593Smuzhiyun 107