1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * OMAP3 OPP table definitions. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/ 5*4882a593Smuzhiyun * Nishanth Menon 6*4882a593Smuzhiyun * Kevin Hilman 7*4882a593Smuzhiyun * Copyright (C) 2010-2011 Nokia Corporation. 8*4882a593Smuzhiyun * Eduardo Valentin 9*4882a593Smuzhiyun * Paul Walmsley 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 12*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 13*4882a593Smuzhiyun * published by the Free Software Foundation. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 16*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty 17*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*4882a593Smuzhiyun * GNU General Public License for more details. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #include <linux/module.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #include "soc.h" 23*4882a593Smuzhiyun #include "control.h" 24*4882a593Smuzhiyun #include "omap_opp_data.h" 25*4882a593Smuzhiyun #include "pm.h" 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 34xx */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* VDD1 */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define OMAP3430_VDD_MPU_OPP1_UV 975000 32*4882a593Smuzhiyun #define OMAP3430_VDD_MPU_OPP2_UV 1075000 33*4882a593Smuzhiyun #define OMAP3430_VDD_MPU_OPP3_UV 1200000 34*4882a593Smuzhiyun #define OMAP3430_VDD_MPU_OPP4_UV 1270000 35*4882a593Smuzhiyun #define OMAP3430_VDD_MPU_OPP5_UV 1350000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct omap_volt_data omap34xx_vddmpu_volt_data[] = { 38*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c), 39*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c), 40*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18), 41*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18), 42*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18), 43*4882a593Smuzhiyun VOLT_DATA_DEFINE(0, 0, 0, 0), 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* VDD2 */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define OMAP3430_VDD_CORE_OPP1_UV 975000 49*4882a593Smuzhiyun #define OMAP3430_VDD_CORE_OPP2_UV 1050000 50*4882a593Smuzhiyun #define OMAP3430_VDD_CORE_OPP3_UV 1150000 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct omap_volt_data omap34xx_vddcore_volt_data[] = { 53*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c), 54*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c), 55*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18), 56*4882a593Smuzhiyun VOLT_DATA_DEFINE(0, 0, 0, 0), 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 36xx */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* VDD1 */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define OMAP3630_VDD_MPU_OPP50_UV 1012500 64*4882a593Smuzhiyun #define OMAP3630_VDD_MPU_OPP100_UV 1200000 65*4882a593Smuzhiyun #define OMAP3630_VDD_MPU_OPP120_UV 1325000 66*4882a593Smuzhiyun #define OMAP3630_VDD_MPU_OPP1G_UV 1375000 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct omap_volt_data omap36xx_vddmpu_volt_data[] = { 69*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c), 70*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16), 71*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23), 72*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27), 73*4882a593Smuzhiyun VOLT_DATA_DEFINE(0, 0, 0, 0), 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* VDD2 */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define OMAP3630_VDD_CORE_OPP50_UV 1000000 79*4882a593Smuzhiyun #define OMAP3630_VDD_CORE_OPP100_UV 1200000 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct omap_volt_data omap36xx_vddcore_volt_data[] = { 82*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c), 83*4882a593Smuzhiyun VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16), 84*4882a593Smuzhiyun VOLT_DATA_DEFINE(0, 0, 0, 0), 85*4882a593Smuzhiyun }; 86