1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /*: 3*4882a593Smuzhiyun * Address mappings and base address for OMAP5 interconnects 4*4882a593Smuzhiyun * and peripherals. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments 7*4882a593Smuzhiyun * Santosh Shilimkar <santosh.shilimkar@ti.com> 8*4882a593Smuzhiyun * Sricharan <r.sricharan@ti.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef __ASM_SOC_OMAP54XX_H 11*4882a593Smuzhiyun #define __ASM_SOC_OMAP54XX_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Please place only base defines here and put the rest in device 15*4882a593Smuzhiyun * specific headers. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define L4_54XX_BASE 0x4a000000 18*4882a593Smuzhiyun #define L4_WK_54XX_BASE 0x4ae00000 19*4882a593Smuzhiyun #define L4_PER_54XX_BASE 0x48000000 20*4882a593Smuzhiyun #define L3_54XX_BASE 0x44000000 21*4882a593Smuzhiyun #define OMAP54XX_32KSYNCT_BASE 0x4ae04000 22*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 23*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_BASE 0x4a008000 24*4882a593Smuzhiyun #define OMAP54XX_PRM_BASE 0x4ae06000 25*4882a593Smuzhiyun #define OMAP54XX_PRCM_MPU_BASE 0x48243000 26*4882a593Smuzhiyun #define OMAP54XX_SCM_BASE 0x4a002000 27*4882a593Smuzhiyun #define OMAP54XX_CTRL_BASE 0x4a002800 28*4882a593Smuzhiyun #define OMAP54XX_SAR_RAM_BASE 0x4ae26000 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* DRA7 specific base addresses */ 31*4882a593Smuzhiyun #define L3_MAIN_SN_DRA7XX_BASE 0x44000000 32*4882a593Smuzhiyun #define L4_PER1_DRA7XX_BASE 0x48000000 33*4882a593Smuzhiyun #define L4_CFG_MPU_DRA7XX_BASE 0x48210000 34*4882a593Smuzhiyun #define L4_PER2_DRA7XX_BASE 0x48400000 35*4882a593Smuzhiyun #define L4_PER3_DRA7XX_BASE 0x48800000 36*4882a593Smuzhiyun #define L4_CFG_DRA7XX_BASE 0x4A000000 37*4882a593Smuzhiyun #define L4_WKUP_DRA7XX_BASE 0x4ae00000 38*4882a593Smuzhiyun #define DRA7XX_CM_CORE_AON_BASE 0x4a005000 39*4882a593Smuzhiyun #define DRA7XX_CTRL_BASE 0x4a003400 40*4882a593Smuzhiyun #define DRA7XX_TAP_BASE 0x4ae0c000 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif /* __ASM_SOC_OMAP555554XX_H */ 43