1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /*: 3*4882a593Smuzhiyun * Address mappings and base address for OMAP4 interconnects 4*4882a593Smuzhiyun * and peripherals. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2009 Texas Instruments 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Santosh Shilimkar <santosh.shilimkar@ti.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_OMAP44XX_H 11*4882a593Smuzhiyun #define __ASM_ARCH_OMAP44XX_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Please place only base defines here and put the rest in device 15*4882a593Smuzhiyun * specific headers. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define L4_44XX_BASE 0x4a000000 18*4882a593Smuzhiyun #define L4_WK_44XX_BASE 0x4a300000 19*4882a593Smuzhiyun #define L4_PER_44XX_BASE 0x48000000 20*4882a593Smuzhiyun #define L4_EMU_44XX_BASE 0x54000000 21*4882a593Smuzhiyun #define L3_44XX_BASE 0x44000000 22*4882a593Smuzhiyun #define OMAP44XX_EMIF1_BASE 0x4c000000 23*4882a593Smuzhiyun #define OMAP44XX_EMIF2_BASE 0x4d000000 24*4882a593Smuzhiyun #define OMAP44XX_DMM_BASE 0x4e000000 25*4882a593Smuzhiyun #define OMAP4430_32KSYNCT_BASE 0x4a304000 26*4882a593Smuzhiyun #define OMAP4430_CM1_BASE 0x4a004000 27*4882a593Smuzhiyun #define OMAP4430_CM_BASE OMAP4430_CM1_BASE 28*4882a593Smuzhiyun #define OMAP4430_CM2_BASE 0x4a008000 29*4882a593Smuzhiyun #define OMAP4430_PRM_BASE 0x4a306000 30*4882a593Smuzhiyun #define OMAP4430_PRCM_MPU_BASE 0x48243000 31*4882a593Smuzhiyun #define OMAP44XX_GPMC_BASE 0x50000000 32*4882a593Smuzhiyun #define OMAP443X_SCM_BASE 0x4a002000 33*4882a593Smuzhiyun #define OMAP443X_CTRL_BASE 0x4a100000 34*4882a593Smuzhiyun #define OMAP44XX_IC_BASE 0x48200000 35*4882a593Smuzhiyun #define OMAP44XX_IVA_INTC_BASE 0x40000000 36*4882a593Smuzhiyun #define IRQ_SIR_IRQ 0x0040 37*4882a593Smuzhiyun #define OMAP44XX_GIC_DIST_BASE 0x48241000 38*4882a593Smuzhiyun #define OMAP44XX_GIC_CPU_BASE 0x48240100 39*4882a593Smuzhiyun #define OMAP44XX_IRQ_GIC_START 32 40*4882a593Smuzhiyun #define OMAP44XX_LOCAL_TWD_BASE 0x48240600 41*4882a593Smuzhiyun #define OMAP44XX_L2CACHE_BASE 0x48242000 42*4882a593Smuzhiyun #define OMAP44XX_WKUPGEN_BASE 0x48281000 43*4882a593Smuzhiyun #define OMAP44XX_MCPDM_BASE 0x40132000 44*4882a593Smuzhiyun #define OMAP44XX_SAR_RAM_BASE 0x4a326000 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000) 47*4882a593Smuzhiyun #define OMAP44XX_HSUSB_OTG_BASE (L4_44XX_BASE + 0xAB000) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define OMAP4_MMU1_BASE 0x55082000 50*4882a593Smuzhiyun #define OMAP4_MMU2_BASE 0x4A066000 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define OMAP44XX_USBTLL_BASE (L4_44XX_BASE + 0x62000) 53*4882a593Smuzhiyun #define OMAP44XX_UHH_CONFIG_BASE (L4_44XX_BASE + 0x64000) 54*4882a593Smuzhiyun #define OMAP44XX_HSUSB_OHCI_BASE (L4_44XX_BASE + 0x64800) 55*4882a593Smuzhiyun #define OMAP44XX_HSUSB_EHCI_BASE (L4_44XX_BASE + 0x64C00) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif /* __ASM_ARCH_OMAP44XX_H */ 58*4882a593Smuzhiyun 59