1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * omap4-sar-layout.h: OMAP4 SAR RAM layout header file 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Texas Instruments, Inc. 6*4882a593Smuzhiyun * Santosh Shilimkar <santosh.shilimkar@ti.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H 9*4882a593Smuzhiyun #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define SAR_BANK1_OFFSET 0x0000 15*4882a593Smuzhiyun #define SAR_BANK2_OFFSET 0x1000 16*4882a593Smuzhiyun #define SAR_BANK3_OFFSET 0x2000 17*4882a593Smuzhiyun #define SAR_BANK4_OFFSET 0x3000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Scratch pad memory offsets from SAR_BANK1 */ 20*4882a593Smuzhiyun #define SCU_OFFSET0 0xfe4 21*4882a593Smuzhiyun #define SCU_OFFSET1 0xfe8 22*4882a593Smuzhiyun #define OMAP_TYPE_OFFSET 0xfec 23*4882a593Smuzhiyun #define L2X0_SAVE_OFFSET0 0xff0 24*4882a593Smuzhiyun #define L2X0_SAVE_OFFSET1 0xff4 25*4882a593Smuzhiyun #define L2X0_AUXCTRL_OFFSET 0xff8 26*4882a593Smuzhiyun #define L2X0_PREFETCH_CTRL_OFFSET 0xffc 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK1 */ 29*4882a593Smuzhiyun #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 30*4882a593Smuzhiyun #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08 31*4882a593Smuzhiyun #define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00 32*4882a593Smuzhiyun #define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xe04 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500) 35*4882a593Smuzhiyun #define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504) 36*4882a593Smuzhiyun #define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */ 39*4882a593Smuzhiyun #define WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x684) 40*4882a593Smuzhiyun #define WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x694) 41*4882a593Smuzhiyun #define WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6a4) 42*4882a593Smuzhiyun #define WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6b4) 43*4882a593Smuzhiyun #define AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x6c4) 44*4882a593Smuzhiyun #define AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x6c8) 45*4882a593Smuzhiyun #define PTMSYNCREQ_MASK_OFFSET (SAR_BANK3_OFFSET + 0x6cc) 46*4882a593Smuzhiyun #define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0) 47*4882a593Smuzhiyun #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ 50*4882a593Smuzhiyun #define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) 51*4882a593Smuzhiyun #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) 52*4882a593Smuzhiyun #define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) 53*4882a593Smuzhiyun #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) 54*4882a593Smuzhiyun #define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) 55*4882a593Smuzhiyun #define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) 56*4882a593Smuzhiyun #define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) 57*4882a593Smuzhiyun #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif 60