1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP44xx CTRL_MODULE_WKUP registers and bitfields 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009-2010 Texas Instruments, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 8*4882a593Smuzhiyun * Santosh Shilimkar (santosh.shilimkar@ti.com) 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 11*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 12*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 13*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 14*4882a593Smuzhiyun * up-to-date with the file contents. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H 18*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Base address */ 22*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP 0x4a30c000 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Registers offset */ 25*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000 26*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004 27*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010 28*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460 29*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464 30*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468 31*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c 32*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470 33*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474 34*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478 35*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c 36*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480 37*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484 38*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488 39*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c 40*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490 41*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494 42*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498 43*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c 44*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0 45*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4 46*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8 47*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac 48*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0 49*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4 50*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8 51*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc 52*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0 53*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4 54*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8 55*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc 56*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0 57*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4 58*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8 59*4882a593Smuzhiyun #define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Registers shifts and masks */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* IP_REVISION */ 64*4882a593Smuzhiyun #define OMAP4_IP_REV_SCHEME_SHIFT 30 65*4882a593Smuzhiyun #define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) 66*4882a593Smuzhiyun #define OMAP4_IP_REV_FUNC_SHIFT 16 67*4882a593Smuzhiyun #define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) 68*4882a593Smuzhiyun #define OMAP4_IP_REV_RTL_SHIFT 11 69*4882a593Smuzhiyun #define OMAP4_IP_REV_RTL_MASK (0x1f << 11) 70*4882a593Smuzhiyun #define OMAP4_IP_REV_MAJOR_SHIFT 8 71*4882a593Smuzhiyun #define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) 72*4882a593Smuzhiyun #define OMAP4_IP_REV_CUSTOM_SHIFT 6 73*4882a593Smuzhiyun #define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) 74*4882a593Smuzhiyun #define OMAP4_IP_REV_MINOR_SHIFT 0 75*4882a593Smuzhiyun #define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* IP_HWINFO */ 78*4882a593Smuzhiyun #define OMAP4_IP_HWINFO_SHIFT 0 79*4882a593Smuzhiyun #define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* IP_SYSCONFIG */ 82*4882a593Smuzhiyun #define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 83*4882a593Smuzhiyun #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* CONF_DEBUG_SEL_TST_0 */ 86*4882a593Smuzhiyun #define OMAP4_WKUP_MODE_SHIFT 0 87*4882a593Smuzhiyun #define OMAP4_WKUP_MODE_MASK (1 << 0) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif 90