1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP2/3 Clock Management (CM) register definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007-2009 Texas Instruments, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2007-2010 Nokia Corporation 7*4882a593Smuzhiyun * Paul Walmsley 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * The CM hardware modules on the OMAP2/3 are quite similar to each 10*4882a593Smuzhiyun * other. The CM modules/instances on OMAP4 are quite different, so 11*4882a593Smuzhiyun * they are handled in a separate file. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H 14*4882a593Smuzhiyun #define __ARCH_ASM_MACH_OMAP2_CM3XXX_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include "prcm-common.h" 17*4882a593Smuzhiyun #include "cm2xxx_3xxx.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define OMAP34XX_CM_REGADDR(module, reg) \ 20*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * OMAP3-specific global CM registers 25*4882a593Smuzhiyun * Use cm_{read,write}_reg() with these registers. 26*4882a593Smuzhiyun * These registers appear once per CM module. 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define OMAP3430_CM_SYSCONFIG 0x0010 30*4882a593Smuzhiyun #define OMAP3430_CM_POLCTRL 0x009c 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 33*4882a593Smuzhiyun #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * Module specific CM register offsets from CM_BASE + domain offset 37*4882a593Smuzhiyun * Use cm_{read,write}_mod_reg() with these registers. 38*4882a593Smuzhiyun * These register offsets generally appear in more than one PRCM submodule. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* OMAP3-specific register offsets */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define OMAP3430_CM_CLKEN_PLL 0x0004 44*4882a593Smuzhiyun #define OMAP3430ES2_CM_CLKEN2 0x0004 45*4882a593Smuzhiyun #define OMAP3430ES2_CM_FCLKEN3 0x0008 46*4882a593Smuzhiyun #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 47*4882a593Smuzhiyun #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 48*4882a593Smuzhiyun #define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 49*4882a593Smuzhiyun #define OMAP3430_CM_CLKSEL1 CM_CLKSEL 50*4882a593Smuzhiyun #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL 51*4882a593Smuzhiyun #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 52*4882a593Smuzhiyun #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 53*4882a593Smuzhiyun #define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL 54*4882a593Smuzhiyun #define OMAP3430_CM_CLKSTST 0x004c 55*4882a593Smuzhiyun #define OMAP3430ES2_CM_CLKSEL4 0x004c 56*4882a593Smuzhiyun #define OMAP3430ES2_CM_CLKSEL5 0x0050 57*4882a593Smuzhiyun #define OMAP3430_CM_CLKSEL2_EMU 0x0050 58*4882a593Smuzhiyun #define OMAP3430_CM_CLKSEL3_EMU 0x0054 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* CM_IDLEST bit field values to indicate deasserted IdleReq */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define OMAP34XX_CM_IDLEST_VAL 1 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #ifndef __ASSEMBLER__ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun extern void omap3_cm_save_context(void); 69*4882a593Smuzhiyun extern void omap3_cm_restore_context(void); 70*4882a593Smuzhiyun extern void omap3_cm_save_scratchpad_contents(u32 *ptr); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data); 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif 77