1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * AM33XX CM offset macros 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 5*4882a593Smuzhiyun * Vaibhav Hiremath <hvaibhav@ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 8*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 9*4882a593Smuzhiyun * published by the Free Software Foundation version 2. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty 13*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*4882a593Smuzhiyun * GNU General Public License for more details. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H 18*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include "cm.h" 21*4882a593Smuzhiyun #include "cm-regbits-33xx.h" 22*4882a593Smuzhiyun #include "prcm-common.h" 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* CM base address */ 25*4882a593Smuzhiyun #define AM33XX_CM_BASE 0x44e00000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define AM33XX_CM_REGADDR(inst, reg) \ 28*4882a593Smuzhiyun AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg)) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* CM instances */ 31*4882a593Smuzhiyun #define AM33XX_CM_PER_MOD 0x0000 32*4882a593Smuzhiyun #define AM33XX_CM_WKUP_MOD 0x0400 33*4882a593Smuzhiyun #define AM33XX_CM_DPLL_MOD 0x0500 34*4882a593Smuzhiyun #define AM33XX_CM_MPU_MOD 0x0600 35*4882a593Smuzhiyun #define AM33XX_CM_DEVICE_MOD 0x0700 36*4882a593Smuzhiyun #define AM33XX_CM_RTC_MOD 0x0800 37*4882a593Smuzhiyun #define AM33XX_CM_GFX_MOD 0x0900 38*4882a593Smuzhiyun #define AM33XX_CM_CEFUSE_MOD 0x0A00 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* CM */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* CM.PER_CM register offsets */ 43*4882a593Smuzhiyun #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000 44*4882a593Smuzhiyun #define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) 45*4882a593Smuzhiyun #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004 46*4882a593Smuzhiyun #define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004) 47*4882a593Smuzhiyun #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008 48*4882a593Smuzhiyun #define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) 49*4882a593Smuzhiyun #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c 50*4882a593Smuzhiyun #define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) 51*4882a593Smuzhiyun #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014 52*4882a593Smuzhiyun #define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014) 53*4882a593Smuzhiyun #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018 54*4882a593Smuzhiyun #define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018) 55*4882a593Smuzhiyun #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c 56*4882a593Smuzhiyun #define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c) 57*4882a593Smuzhiyun #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020 58*4882a593Smuzhiyun #define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020) 59*4882a593Smuzhiyun #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024 60*4882a593Smuzhiyun #define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024) 61*4882a593Smuzhiyun #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028 62*4882a593Smuzhiyun #define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) 63*4882a593Smuzhiyun #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c 64*4882a593Smuzhiyun #define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c) 65*4882a593Smuzhiyun #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030 66*4882a593Smuzhiyun #define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030) 67*4882a593Smuzhiyun #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034 68*4882a593Smuzhiyun #define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034) 69*4882a593Smuzhiyun #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038 70*4882a593Smuzhiyun #define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038) 71*4882a593Smuzhiyun #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c 72*4882a593Smuzhiyun #define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c) 73*4882a593Smuzhiyun #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040 74*4882a593Smuzhiyun #define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040) 75*4882a593Smuzhiyun #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044 76*4882a593Smuzhiyun #define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044) 77*4882a593Smuzhiyun #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048 78*4882a593Smuzhiyun #define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048) 79*4882a593Smuzhiyun #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c 80*4882a593Smuzhiyun #define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c) 81*4882a593Smuzhiyun #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050 82*4882a593Smuzhiyun #define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050) 83*4882a593Smuzhiyun #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054 84*4882a593Smuzhiyun #define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054) 85*4882a593Smuzhiyun #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058 86*4882a593Smuzhiyun #define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058) 87*4882a593Smuzhiyun #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060 88*4882a593Smuzhiyun #define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060) 89*4882a593Smuzhiyun #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064 90*4882a593Smuzhiyun #define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064) 91*4882a593Smuzhiyun #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068 92*4882a593Smuzhiyun #define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068) 93*4882a593Smuzhiyun #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c 94*4882a593Smuzhiyun #define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c) 95*4882a593Smuzhiyun #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070 96*4882a593Smuzhiyun #define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070) 97*4882a593Smuzhiyun #define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074 98*4882a593Smuzhiyun #define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074) 99*4882a593Smuzhiyun #define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078 100*4882a593Smuzhiyun #define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078) 101*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c 102*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c) 103*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080 104*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080) 105*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084 106*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084) 107*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088 108*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088) 109*4882a593Smuzhiyun #define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c 110*4882a593Smuzhiyun #define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c) 111*4882a593Smuzhiyun #define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090 112*4882a593Smuzhiyun #define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090) 113*4882a593Smuzhiyun #define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094 114*4882a593Smuzhiyun #define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094) 115*4882a593Smuzhiyun #define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098 116*4882a593Smuzhiyun #define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098) 117*4882a593Smuzhiyun #define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c 118*4882a593Smuzhiyun #define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c) 119*4882a593Smuzhiyun #define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0 120*4882a593Smuzhiyun #define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0) 121*4882a593Smuzhiyun #define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4 122*4882a593Smuzhiyun #define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4) 123*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8 124*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8) 125*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac 126*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac) 127*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0 128*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0) 129*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4 130*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4) 131*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8 132*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8) 133*4882a593Smuzhiyun #define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc 134*4882a593Smuzhiyun #define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc) 135*4882a593Smuzhiyun #define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0 136*4882a593Smuzhiyun #define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0) 137*4882a593Smuzhiyun #define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4 138*4882a593Smuzhiyun #define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4) 139*4882a593Smuzhiyun #define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc 140*4882a593Smuzhiyun #define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc) 141*4882a593Smuzhiyun #define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0 142*4882a593Smuzhiyun #define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0) 143*4882a593Smuzhiyun #define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4 144*4882a593Smuzhiyun #define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4) 145*4882a593Smuzhiyun #define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8 146*4882a593Smuzhiyun #define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8) 147*4882a593Smuzhiyun #define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc 148*4882a593Smuzhiyun #define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc) 149*4882a593Smuzhiyun #define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0 150*4882a593Smuzhiyun #define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0) 151*4882a593Smuzhiyun #define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4 152*4882a593Smuzhiyun #define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4) 153*4882a593Smuzhiyun #define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8 154*4882a593Smuzhiyun #define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8) 155*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec 156*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec) 157*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0 158*4882a593Smuzhiyun #define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0) 159*4882a593Smuzhiyun #define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4 160*4882a593Smuzhiyun #define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4) 161*4882a593Smuzhiyun #define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8 162*4882a593Smuzhiyun #define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8) 163*4882a593Smuzhiyun #define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc 164*4882a593Smuzhiyun #define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc) 165*4882a593Smuzhiyun #define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100 166*4882a593Smuzhiyun #define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100) 167*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104 168*4882a593Smuzhiyun #define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104) 169*4882a593Smuzhiyun #define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c 170*4882a593Smuzhiyun #define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c) 171*4882a593Smuzhiyun #define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110 172*4882a593Smuzhiyun #define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110) 173*4882a593Smuzhiyun #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c 174*4882a593Smuzhiyun #define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c) 175*4882a593Smuzhiyun #define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120 176*4882a593Smuzhiyun #define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120) 177*4882a593Smuzhiyun #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124 178*4882a593Smuzhiyun #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124) 179*4882a593Smuzhiyun #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128 180*4882a593Smuzhiyun #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128) 181*4882a593Smuzhiyun #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c 182*4882a593Smuzhiyun #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c) 183*4882a593Smuzhiyun #define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130 184*4882a593Smuzhiyun #define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130) 185*4882a593Smuzhiyun #define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134 186*4882a593Smuzhiyun #define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134) 187*4882a593Smuzhiyun #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140 188*4882a593Smuzhiyun #define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140) 189*4882a593Smuzhiyun #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144 190*4882a593Smuzhiyun #define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144) 191*4882a593Smuzhiyun #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148 192*4882a593Smuzhiyun #define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148) 193*4882a593Smuzhiyun #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c 194*4882a593Smuzhiyun #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c) 195*4882a593Smuzhiyun #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150 196*4882a593Smuzhiyun #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150) 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* CM.WKUP_CM register offsets */ 199*4882a593Smuzhiyun #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 200*4882a593Smuzhiyun #define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000) 201*4882a593Smuzhiyun #define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004 202*4882a593Smuzhiyun #define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004) 203*4882a593Smuzhiyun #define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008 204*4882a593Smuzhiyun #define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008) 205*4882a593Smuzhiyun #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c 206*4882a593Smuzhiyun #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c) 207*4882a593Smuzhiyun #define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010 208*4882a593Smuzhiyun #define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010) 209*4882a593Smuzhiyun #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014 210*4882a593Smuzhiyun #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014) 211*4882a593Smuzhiyun #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018 212*4882a593Smuzhiyun #define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018) 213*4882a593Smuzhiyun #define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c 214*4882a593Smuzhiyun #define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c) 215*4882a593Smuzhiyun #define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020 216*4882a593Smuzhiyun #define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020) 217*4882a593Smuzhiyun #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024 218*4882a593Smuzhiyun #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024) 219*4882a593Smuzhiyun #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028 220*4882a593Smuzhiyun #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028) 221*4882a593Smuzhiyun #define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c 222*4882a593Smuzhiyun #define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c) 223*4882a593Smuzhiyun #define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030 224*4882a593Smuzhiyun #define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030) 225*4882a593Smuzhiyun #define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034 226*4882a593Smuzhiyun #define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034) 227*4882a593Smuzhiyun #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038 228*4882a593Smuzhiyun #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038) 229*4882a593Smuzhiyun #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c 230*4882a593Smuzhiyun #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c) 231*4882a593Smuzhiyun #define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040 232*4882a593Smuzhiyun #define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040) 233*4882a593Smuzhiyun #define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044 234*4882a593Smuzhiyun #define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044) 235*4882a593Smuzhiyun #define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048 236*4882a593Smuzhiyun #define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048) 237*4882a593Smuzhiyun #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c 238*4882a593Smuzhiyun #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c) 239*4882a593Smuzhiyun #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050 240*4882a593Smuzhiyun #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050) 241*4882a593Smuzhiyun #define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054 242*4882a593Smuzhiyun #define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054) 243*4882a593Smuzhiyun #define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058 244*4882a593Smuzhiyun #define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058) 245*4882a593Smuzhiyun #define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c 246*4882a593Smuzhiyun #define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c) 247*4882a593Smuzhiyun #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060 248*4882a593Smuzhiyun #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060) 249*4882a593Smuzhiyun #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064 250*4882a593Smuzhiyun #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064) 251*4882a593Smuzhiyun #define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068 252*4882a593Smuzhiyun #define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068) 253*4882a593Smuzhiyun #define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c 254*4882a593Smuzhiyun #define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c) 255*4882a593Smuzhiyun #define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070 256*4882a593Smuzhiyun #define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070) 257*4882a593Smuzhiyun #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074 258*4882a593Smuzhiyun #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074) 259*4882a593Smuzhiyun #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078 260*4882a593Smuzhiyun #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078) 261*4882a593Smuzhiyun #define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c 262*4882a593Smuzhiyun #define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c) 263*4882a593Smuzhiyun #define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080 264*4882a593Smuzhiyun #define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080) 265*4882a593Smuzhiyun #define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084 266*4882a593Smuzhiyun #define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084) 267*4882a593Smuzhiyun #define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088 268*4882a593Smuzhiyun #define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088) 269*4882a593Smuzhiyun #define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c 270*4882a593Smuzhiyun #define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c) 271*4882a593Smuzhiyun #define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090 272*4882a593Smuzhiyun #define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090) 273*4882a593Smuzhiyun #define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094 274*4882a593Smuzhiyun #define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094) 275*4882a593Smuzhiyun #define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098 276*4882a593Smuzhiyun #define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098) 277*4882a593Smuzhiyun #define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c 278*4882a593Smuzhiyun #define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c) 279*4882a593Smuzhiyun #define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0 280*4882a593Smuzhiyun #define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0) 281*4882a593Smuzhiyun #define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4 282*4882a593Smuzhiyun #define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4) 283*4882a593Smuzhiyun #define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8 284*4882a593Smuzhiyun #define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8) 285*4882a593Smuzhiyun #define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac 286*4882a593Smuzhiyun #define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac) 287*4882a593Smuzhiyun #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0 288*4882a593Smuzhiyun #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0) 289*4882a593Smuzhiyun #define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4 290*4882a593Smuzhiyun #define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4) 291*4882a593Smuzhiyun #define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8 292*4882a593Smuzhiyun #define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8) 293*4882a593Smuzhiyun #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc 294*4882a593Smuzhiyun #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc) 295*4882a593Smuzhiyun #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0 296*4882a593Smuzhiyun #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0) 297*4882a593Smuzhiyun #define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4 298*4882a593Smuzhiyun #define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4) 299*4882a593Smuzhiyun #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8 300*4882a593Smuzhiyun #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8) 301*4882a593Smuzhiyun #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc 302*4882a593Smuzhiyun #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc) 303*4882a593Smuzhiyun #define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0 304*4882a593Smuzhiyun #define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0) 305*4882a593Smuzhiyun #define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4 306*4882a593Smuzhiyun #define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4) 307*4882a593Smuzhiyun #define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8 308*4882a593Smuzhiyun #define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8) 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* CM.DPLL_CM register offsets */ 311*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004 312*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004) 313*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008 314*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008) 315*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c 316*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c) 317*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010 318*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010) 319*4882a593Smuzhiyun #define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014 320*4882a593Smuzhiyun #define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014) 321*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018 322*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018) 323*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c 324*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c) 325*4882a593Smuzhiyun #define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020 326*4882a593Smuzhiyun #define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020) 327*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028 328*4882a593Smuzhiyun #define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028) 329*4882a593Smuzhiyun #define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c 330*4882a593Smuzhiyun #define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) 331*4882a593Smuzhiyun #define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030 332*4882a593Smuzhiyun #define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030) 333*4882a593Smuzhiyun #define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034 334*4882a593Smuzhiyun #define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034) 335*4882a593Smuzhiyun #define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038 336*4882a593Smuzhiyun #define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038) 337*4882a593Smuzhiyun #define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c 338*4882a593Smuzhiyun #define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c) 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* CM.MPU_CM register offsets */ 341*4882a593Smuzhiyun #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 342*4882a593Smuzhiyun #define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000) 343*4882a593Smuzhiyun #define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004 344*4882a593Smuzhiyun #define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004) 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun /* CM.DEVICE_CM register offsets */ 347*4882a593Smuzhiyun #define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000 348*4882a593Smuzhiyun #define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000) 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun /* CM.RTC_CM register offsets */ 351*4882a593Smuzhiyun #define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000 352*4882a593Smuzhiyun #define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000) 353*4882a593Smuzhiyun #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004 354*4882a593Smuzhiyun #define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004) 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun /* CM.GFX_CM register offsets */ 357*4882a593Smuzhiyun #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000 358*4882a593Smuzhiyun #define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000) 359*4882a593Smuzhiyun #define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004 360*4882a593Smuzhiyun #define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004) 361*4882a593Smuzhiyun #define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008 362*4882a593Smuzhiyun #define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008) 363*4882a593Smuzhiyun #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c 364*4882a593Smuzhiyun #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c) 365*4882a593Smuzhiyun #define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010 366*4882a593Smuzhiyun #define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010) 367*4882a593Smuzhiyun #define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014 368*4882a593Smuzhiyun #define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014) 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun /* CM.CEFUSE_CM register offsets */ 371*4882a593Smuzhiyun #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 372*4882a593Smuzhiyun #define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000) 373*4882a593Smuzhiyun #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 374*4882a593Smuzhiyun #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun #ifndef __ASSEMBLER__ 378*4882a593Smuzhiyun int am33xx_cm_init(const struct omap_prcm_init_data *data); 379*4882a593Smuzhiyun #endif /* ASSEMBLER */ 380*4882a593Smuzhiyun #endif 381