1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * OMAP2/3 Clock Management (CM) register definitions
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2007-2009 Texas Instruments, Inc.
6*4882a593Smuzhiyun * Copyright (C) 2007-2010 Nokia Corporation
7*4882a593Smuzhiyun * Paul Walmsley
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * The CM hardware modules on the OMAP2/3 are quite similar to each
10*4882a593Smuzhiyun * other. The CM modules/instances on OMAP4 are quite different, so
11*4882a593Smuzhiyun * they are handled in a separate file.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
14*4882a593Smuzhiyun #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "cm.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * Module specific CM register offsets from CM_BASE + domain offset
20*4882a593Smuzhiyun * Use cm_{read,write}_mod_reg() with these registers.
21*4882a593Smuzhiyun * These register offsets generally appear in more than one PRCM submodule.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Common between OMAP2 and OMAP3 */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define CM_FCLKEN 0x0000
27*4882a593Smuzhiyun #define CM_FCLKEN1 CM_FCLKEN
28*4882a593Smuzhiyun #define CM_CLKEN CM_FCLKEN
29*4882a593Smuzhiyun #define CM_ICLKEN 0x0010
30*4882a593Smuzhiyun #define CM_ICLKEN1 CM_ICLKEN
31*4882a593Smuzhiyun #define CM_ICLKEN2 0x0014
32*4882a593Smuzhiyun #define CM_ICLKEN3 0x0018
33*4882a593Smuzhiyun #define CM_IDLEST 0x0020
34*4882a593Smuzhiyun #define CM_IDLEST1 CM_IDLEST
35*4882a593Smuzhiyun #define CM_IDLEST2 0x0024
36*4882a593Smuzhiyun #define OMAP2430_CM_IDLEST3 0x0028
37*4882a593Smuzhiyun #define CM_AUTOIDLE 0x0030
38*4882a593Smuzhiyun #define CM_AUTOIDLE1 CM_AUTOIDLE
39*4882a593Smuzhiyun #define CM_AUTOIDLE2 0x0034
40*4882a593Smuzhiyun #define CM_AUTOIDLE3 0x0038
41*4882a593Smuzhiyun #define CM_CLKSEL 0x0040
42*4882a593Smuzhiyun #define CM_CLKSEL1 CM_CLKSEL
43*4882a593Smuzhiyun #define CM_CLKSEL2 0x0044
44*4882a593Smuzhiyun #define OMAP2_CM_CLKSTCTRL 0x0048
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #ifndef __ASSEMBLER__
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #include <linux/io.h>
49*4882a593Smuzhiyun
omap2_cm_read_mod_reg(s16 module,u16 idx)50*4882a593Smuzhiyun static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun return readl_relaxed(cm_base.va + module + idx);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
omap2_cm_write_mod_reg(u32 val,s16 module,u16 idx)55*4882a593Smuzhiyun static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun writel_relaxed(val, cm_base.va + module + idx);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Read-modify-write a register in a CM module. Caller must lock */
omap2_cm_rmw_mod_reg_bits(u32 mask,u32 bits,s16 module,s16 idx)61*4882a593Smuzhiyun static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
62*4882a593Smuzhiyun s16 idx)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun u32 v;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun v = omap2_cm_read_mod_reg(module, idx);
67*4882a593Smuzhiyun v &= ~mask;
68*4882a593Smuzhiyun v |= bits;
69*4882a593Smuzhiyun omap2_cm_write_mod_reg(v, module, idx);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return v;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Read a CM register, AND it, and shift the result down to bit 0 */
omap2_cm_read_mod_bits_shift(s16 domain,s16 idx,u32 mask)75*4882a593Smuzhiyun static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun u32 v;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun v = omap2_cm_read_mod_reg(domain, idx);
80*4882a593Smuzhiyun v &= mask;
81*4882a593Smuzhiyun v >>= __ffs(mask);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return v;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
omap2_cm_set_mod_reg_bits(u32 bits,s16 module,s16 idx)86*4882a593Smuzhiyun static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
omap2_cm_clear_mod_reg_bits(u32 bits,s16 module,s16 idx)91*4882a593Smuzhiyun static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun extern int omap2xxx_cm_apll54_enable(void);
97*4882a593Smuzhiyun extern void omap2xxx_cm_apll54_disable(void);
98*4882a593Smuzhiyun extern int omap2xxx_cm_apll96_enable(void);
99*4882a593Smuzhiyun extern void omap2xxx_cm_apll96_disable(void);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #endif
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* CM register bits shared between 24XX and 3430 */
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* CM_CLKSEL_GFX */
106*4882a593Smuzhiyun #define OMAP_CLKSEL_GFX_SHIFT 0
107*4882a593Smuzhiyun #define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
108*4882a593Smuzhiyun #define OMAP_CLKSEL_GFX_WIDTH 3
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* CM_ICLKEN_GFX */
111*4882a593Smuzhiyun #define OMAP_EN_GFX_SHIFT 0
112*4882a593Smuzhiyun #define OMAP_EN_GFX_MASK (1 << 0)
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* CM_IDLEST_GFX */
115*4882a593Smuzhiyun #define OMAP_ST_GFX_MASK (1 << 0)
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #endif
118