1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP2xxx Clock Management (CM) register definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2007-2010 Nokia Corporation 7*4882a593Smuzhiyun * Paul Walmsley 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * The CM hardware modules on the OMAP2/3 are quite similar to each 10*4882a593Smuzhiyun * other. The CM modules/instances on OMAP4 are quite different, so 11*4882a593Smuzhiyun * they are handled in a separate file. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H 14*4882a593Smuzhiyun #define __ARCH_ASM_MACH_OMAP2_CM2XXX_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include "prcm-common.h" 17*4882a593Smuzhiyun #include "cm2xxx_3xxx.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define OMAP2420_CM_REGADDR(module, reg) \ 20*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) 21*4882a593Smuzhiyun #define OMAP2430_CM_REGADDR(module, reg) \ 22*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * Module specific CM register offsets from CM_BASE + domain offset 26*4882a593Smuzhiyun * Use cm_{read,write}_mod_reg() with these registers. 27*4882a593Smuzhiyun * These register offsets generally appear in more than one PRCM submodule. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* OMAP2-specific register offsets */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define OMAP24XX_CM_FCLKEN2 0x0004 33*4882a593Smuzhiyun #define OMAP24XX_CM_ICLKEN4 0x001c 34*4882a593Smuzhiyun #define OMAP24XX_CM_AUTOIDLE4 0x003c 35*4882a593Smuzhiyun #define OMAP24XX_CM_IDLEST4 0x002c 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* CM_IDLEST bit field values to indicate deasserted IdleReq */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define OMAP24XX_CM_IDLEST_VAL 0 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Clock management domain register get/set */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #ifndef __ASSEMBLER__ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun extern void omap2xxx_cm_set_dpll_disable_autoidle(void); 47*4882a593Smuzhiyun extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun extern void omap2xxx_cm_set_apll54_disable_autoidle(void); 50*4882a593Smuzhiyun extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void); 51*4882a593Smuzhiyun extern void omap2xxx_cm_set_apll96_disable_autoidle(void); 52*4882a593Smuzhiyun extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id, 55*4882a593Smuzhiyun u8 idlest_shift); 56*4882a593Smuzhiyun extern int omap2xxx_cm_fclks_active(void); 57*4882a593Smuzhiyun extern int omap2xxx_cm_mpu_retention_allowed(void); 58*4882a593Smuzhiyun extern u32 omap2xxx_cm_get_core_clk_src(void); 59*4882a593Smuzhiyun extern u32 omap2xxx_cm_get_core_pll_config(void); 60*4882a593Smuzhiyun extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, 61*4882a593Smuzhiyun u32 mdm); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #endif 68