1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP54xx CM2 instance offset macros 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Paul Walmsley (paul@pwsan.com) 8*4882a593Smuzhiyun * Rajendra Nayak (rnayak@ti.com) 9*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 12*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 13*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 14*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 15*4882a593Smuzhiyun * up-to-date with the file contents. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 19*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* CM2 base address */ 22*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_BASE 0x4a008000 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_REGADDR(inst, reg) \ 25*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg)) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* CM_CORE instances */ 28*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000 29*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100 30*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_COREAON_INST 0x0600 31*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_INST 0x0700 32*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_IVA_INST 0x1200 33*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CAM_INST 0x1300 34*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_DSS_INST 0x1400 35*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_GPU_INST 0x1500 36*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600 37*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700 38*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_RESTORE_INST 0x1e00 39*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_INSTR_INST 0x1f00 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* CM_CORE clockdomain register offsets (from instance start) */ 42*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 43*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 44*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100 45*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200 46*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 47*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 48*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500 49*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 50*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 51*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800 52*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900 53*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80 54*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 55*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 56*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 57*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 58*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 59*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* CM_CORE */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ 64*4882a593Smuzhiyun #define OMAP54XX_REVISION_CM_CORE_OFFSET 0x0000 65*4882a593Smuzhiyun #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 66*4882a593Smuzhiyun #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040) 67*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET 0x0080 68*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET 0x0084 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* CM_CORE.CKGEN_CM_CORE register offsets */ 71*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 72*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_USB_60MHZ OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004) 73*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 74*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040) 75*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET 0x0044 76*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044) 77*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 78*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048) 79*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET 0x004c 80*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c) 81*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 82*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050) 83*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 84*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M3_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054) 85*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0058 86*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H11_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058) 87*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET 0x005c 88*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H12_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c) 89*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET 0x0060 90*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H13_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060) 91*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0064 92*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H14_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064) 93*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 94*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c 95*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 96*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080) 97*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET 0x0084 98*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084) 99*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 100*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088) 101*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET 0x008c 102*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c) 103*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 104*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090) 105*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 106*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac 107*4882a593Smuzhiyun #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 108*4882a593Smuzhiyun #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4) 109*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET 0x00c0 110*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0) 111*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET 0x00c4 112*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4) 113*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET 0x00c8 114*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8) 115*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET 0x00cc 116*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc) 117*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET 0x00d0 118*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0) 119*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET 0x00e8 120*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET 0x00ec 121*4882a593Smuzhiyun #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET 0x00f4 122*4882a593Smuzhiyun #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4) 123*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET 0x0100 124*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100) 125*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET 0x0104 126*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104) 127*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET 0x0108 128*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108) 129*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET 0x010c 130*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c) 131*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET 0x0110 132*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110) 133*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET 0x0128 134*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET 0x012c 135*4882a593Smuzhiyun #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET 0x0134 136*4882a593Smuzhiyun #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134) 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* CM_CORE.COREAON_CM_CORE register offsets */ 139*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 140*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 141*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028) 142*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET 0x0030 143*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030) 144*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 145*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038) 146*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET 0x0040 147*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040) 148*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 149*4882a593Smuzhiyun #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* CM_CORE.CORE_CM_CORE register offsets */ 152*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 153*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 154*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 155*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020) 156*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET 0x0100 157*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET 0x0108 158*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET 0x0120 159*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120) 160*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET 0x0128 161*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128) 162*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 163*4882a593Smuzhiyun #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130) 164*4882a593Smuzhiyun #define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET 0x0200 165*4882a593Smuzhiyun #define OMAP54XX_CM_IPU_STATICDEP_OFFSET 0x0204 166*4882a593Smuzhiyun #define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET 0x0208 167*4882a593Smuzhiyun #define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET 0x0220 168*4882a593Smuzhiyun #define OMAP54XX_CM_IPU_IPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220) 169*4882a593Smuzhiyun #define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 170*4882a593Smuzhiyun #define OMAP54XX_CM_DMA_STATICDEP_OFFSET 0x0304 171*4882a593Smuzhiyun #define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 172*4882a593Smuzhiyun #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 173*4882a593Smuzhiyun #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320) 174*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 175*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 176*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_DMM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420) 177*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 178*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428) 179*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 180*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430) 181*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 182*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438) 183*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 184*4882a593Smuzhiyun #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440) 185*4882a593Smuzhiyun #define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET 0x0500 186*4882a593Smuzhiyun #define OMAP54XX_CM_C2C_STATICDEP_OFFSET 0x0504 187*4882a593Smuzhiyun #define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET 0x0508 188*4882a593Smuzhiyun #define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET 0x0520 189*4882a593Smuzhiyun #define OMAP54XX_CM_C2C_C2C_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520) 190*4882a593Smuzhiyun #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET 0x0528 191*4882a593Smuzhiyun #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528) 192*4882a593Smuzhiyun #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET 0x0530 193*4882a593Smuzhiyun #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530) 194*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 195*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 196*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 197*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620) 198*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 199*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628) 200*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 201*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630) 202*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 203*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638) 204*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 205*4882a593Smuzhiyun #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640) 206*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 207*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET 0x0720 208*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720) 209*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 210*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728) 211*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 212*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740) 213*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 214*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748) 215*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 216*4882a593Smuzhiyun #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750) 217*4882a593Smuzhiyun #define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET 0x0800 218*4882a593Smuzhiyun #define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET 0x0804 219*4882a593Smuzhiyun #define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET 0x0808 220*4882a593Smuzhiyun #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET 0x0820 221*4882a593Smuzhiyun #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820) 222*4882a593Smuzhiyun #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET 0x0828 223*4882a593Smuzhiyun #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828) 224*4882a593Smuzhiyun #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET 0x0830 225*4882a593Smuzhiyun #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830) 226*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0900 227*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0908 228*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0928 229*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928) 230*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0930 231*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930) 232*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0938 233*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938) 234*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0940 235*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940) 236*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0948 237*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948) 238*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0950 239*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950) 240*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0958 241*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_ELM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958) 242*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0960 243*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960) 244*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0968 245*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968) 246*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0970 247*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970) 248*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0978 249*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978) 250*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0980 251*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980) 252*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0988 253*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988) 254*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x09a0 255*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0) 256*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x09a8 257*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8) 258*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x09b0 259*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0) 260*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x09b8 261*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8) 262*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET 0x09c0 263*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0) 264*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x09f0 265*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0) 266*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x09f8 267*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8) 268*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0a00 269*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00) 270*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0a08 271*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08) 272*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0a10 273*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10) 274*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0a18 275*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18) 276*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0a20 277*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20) 278*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0a28 279*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28) 280*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0a40 281*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40) 282*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0a48 283*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48) 284*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0a50 285*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50) 286*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0a58 287*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58) 288*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET 0x0a60 289*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60) 290*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0a68 291*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68) 292*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0a70 293*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70) 294*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET 0x0a78 295*4882a593Smuzhiyun #define OMAP54XX_CM_L4PER_UART6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78) 296*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0a80 297*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET 0x0a84 298*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0a88 299*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x0aa0 300*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0) 301*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x0aa8 302*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8) 303*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x0ab0 304*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0) 305*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x0ab8 306*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8) 307*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x0ac0 308*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0) 309*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET 0x0ac8 310*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8) 311*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x0ad8 312*4882a593Smuzhiyun #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8) 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* CM_CORE.IVA_CM_CORE register offsets */ 315*4882a593Smuzhiyun #define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 316*4882a593Smuzhiyun #define OMAP54XX_CM_IVA_STATICDEP_OFFSET 0x0004 317*4882a593Smuzhiyun #define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 318*4882a593Smuzhiyun #define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 319*4882a593Smuzhiyun #define OMAP54XX_CM_IVA_IVA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020) 320*4882a593Smuzhiyun #define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 321*4882a593Smuzhiyun #define OMAP54XX_CM_IVA_SL2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028) 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun /* CM_CORE.CAM_CM_CORE register offsets */ 324*4882a593Smuzhiyun #define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 325*4882a593Smuzhiyun #define OMAP54XX_CM_CAM_STATICDEP_OFFSET 0x0004 326*4882a593Smuzhiyun #define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET 0x0008 327*4882a593Smuzhiyun #define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 328*4882a593Smuzhiyun #define OMAP54XX_CM_CAM_ISS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020) 329*4882a593Smuzhiyun #define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 330*4882a593Smuzhiyun #define OMAP54XX_CM_CAM_FDIF_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028) 331*4882a593Smuzhiyun #define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET 0x0030 332*4882a593Smuzhiyun #define OMAP54XX_CM_CAM_CAL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030) 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun /* CM_CORE.DSS_CM_CORE register offsets */ 335*4882a593Smuzhiyun #define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 336*4882a593Smuzhiyun #define OMAP54XX_CM_DSS_STATICDEP_OFFSET 0x0004 337*4882a593Smuzhiyun #define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 338*4882a593Smuzhiyun #define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 339*4882a593Smuzhiyun #define OMAP54XX_CM_DSS_DSS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020) 340*4882a593Smuzhiyun #define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 341*4882a593Smuzhiyun #define OMAP54XX_CM_DSS_BB2D_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030) 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun /* CM_CORE.GPU_CM_CORE register offsets */ 344*4882a593Smuzhiyun #define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 345*4882a593Smuzhiyun #define OMAP54XX_CM_GPU_STATICDEP_OFFSET 0x0004 346*4882a593Smuzhiyun #define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 347*4882a593Smuzhiyun #define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 348*4882a593Smuzhiyun #define OMAP54XX_CM_GPU_GPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020) 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun /* CM_CORE.L3INIT_CM_CORE register offsets */ 351*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 352*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 353*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 354*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 355*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028) 356*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 357*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030) 358*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 359*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038) 360*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET 0x0040 361*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040) 362*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET 0x0048 363*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048) 364*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET 0x0058 365*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058) 366*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET 0x0068 367*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068) 368*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 369*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078) 370*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 371*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088) 372*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 373*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0) 374*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 375*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8) 376*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET 0x00f0 377*4882a593Smuzhiyun #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0) 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ 380*4882a593Smuzhiyun #define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 381*4882a593Smuzhiyun #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 382*4882a593Smuzhiyun #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020) 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun #endif 385