1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP44xx CM2 instance offset macros 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009-2011 Texas Instruments, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2009-2010 Nokia Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Paul Walmsley (paul@pwsan.com) 9*4882a593Smuzhiyun * Rajendra Nayak (rnayak@ti.com) 10*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 13*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 14*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 15*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 16*4882a593Smuzhiyun * up-to-date with the file contents. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 19*4882a593Smuzhiyun * or "OMAP4430". 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 23*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* CM2 base address */ 26*4882a593Smuzhiyun #define OMAP4430_CM2_BASE 0x4a008000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define OMAP44XX_CM2_REGADDR(inst, reg) \ 29*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg)) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* CM2 instances */ 32*4882a593Smuzhiyun #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000 33*4882a593Smuzhiyun #define OMAP4430_CM2_CKGEN_INST 0x0100 34*4882a593Smuzhiyun #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600 35*4882a593Smuzhiyun #define OMAP4430_CM2_CORE_INST 0x0700 36*4882a593Smuzhiyun #define OMAP4430_CM2_IVAHD_INST 0x0f00 37*4882a593Smuzhiyun #define OMAP4430_CM2_CAM_INST 0x1000 38*4882a593Smuzhiyun #define OMAP4430_CM2_DSS_INST 0x1100 39*4882a593Smuzhiyun #define OMAP4430_CM2_GFX_INST 0x1200 40*4882a593Smuzhiyun #define OMAP4430_CM2_L3INIT_INST 0x1300 41*4882a593Smuzhiyun #define OMAP4430_CM2_L4PER_INST 0x1400 42*4882a593Smuzhiyun #define OMAP4430_CM2_CEFUSE_INST 0x1600 43*4882a593Smuzhiyun #define OMAP4430_CM2_RESTORE_INST 0x1e00 44*4882a593Smuzhiyun #define OMAP4430_CM2_INSTR_INST 0x1f00 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* CM2 clockdomain register offsets (from instance start) */ 47*4882a593Smuzhiyun #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 48*4882a593Smuzhiyun #define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000 49*4882a593Smuzhiyun #define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100 50*4882a593Smuzhiyun #define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200 51*4882a593Smuzhiyun #define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300 52*4882a593Smuzhiyun #define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400 53*4882a593Smuzhiyun #define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500 54*4882a593Smuzhiyun #define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600 55*4882a593Smuzhiyun #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700 56*4882a593Smuzhiyun #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000 57*4882a593Smuzhiyun #define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000 58*4882a593Smuzhiyun #define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000 59*4882a593Smuzhiyun #define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000 60*4882a593Smuzhiyun #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000 61*4882a593Smuzhiyun #define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000 62*4882a593Smuzhiyun #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 63*4882a593Smuzhiyun #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* CM2 */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* CM2.OCP_SOCKET_CM2 register offsets */ 68*4882a593Smuzhiyun #define OMAP4_REVISION_CM2_OFFSET 0x0000 69*4882a593Smuzhiyun #define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000) 70*4882a593Smuzhiyun #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 71*4882a593Smuzhiyun #define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* CM2.CKGEN_CM2 register offsets */ 74*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 75*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000) 76*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 77*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004) 78*4882a593Smuzhiyun #define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 79*4882a593Smuzhiyun #define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008) 80*4882a593Smuzhiyun #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 81*4882a593Smuzhiyun #define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010) 82*4882a593Smuzhiyun #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 83*4882a593Smuzhiyun #define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014) 84*4882a593Smuzhiyun #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 85*4882a593Smuzhiyun #define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018) 86*4882a593Smuzhiyun #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c 87*4882a593Smuzhiyun #define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c) 88*4882a593Smuzhiyun #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 89*4882a593Smuzhiyun #define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024) 90*4882a593Smuzhiyun #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 91*4882a593Smuzhiyun #define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028) 92*4882a593Smuzhiyun #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c 93*4882a593Smuzhiyun #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c) 94*4882a593Smuzhiyun #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 95*4882a593Smuzhiyun #define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030) 96*4882a593Smuzhiyun #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 97*4882a593Smuzhiyun #define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038) 98*4882a593Smuzhiyun #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 99*4882a593Smuzhiyun #define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040) 100*4882a593Smuzhiyun #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 101*4882a593Smuzhiyun #define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044) 102*4882a593Smuzhiyun #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 103*4882a593Smuzhiyun #define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048) 104*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c 105*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c) 106*4882a593Smuzhiyun #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 107*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050) 108*4882a593Smuzhiyun #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 109*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054) 110*4882a593Smuzhiyun #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 111*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058) 112*4882a593Smuzhiyun #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c 113*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c) 114*4882a593Smuzhiyun #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 115*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060) 116*4882a593Smuzhiyun #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 117*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) 118*4882a593Smuzhiyun #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 119*4882a593Smuzhiyun #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) 120*4882a593Smuzhiyun #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c 121*4882a593Smuzhiyun #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) 122*4882a593Smuzhiyun #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 123*4882a593Smuzhiyun #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) 124*4882a593Smuzhiyun #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 125*4882a593Smuzhiyun #define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084) 126*4882a593Smuzhiyun #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 127*4882a593Smuzhiyun #define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088) 128*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c 129*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c) 130*4882a593Smuzhiyun #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 131*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) 132*4882a593Smuzhiyun #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 133*4882a593Smuzhiyun #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) 134*4882a593Smuzhiyun #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac 135*4882a593Smuzhiyun #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) 136*4882a593Smuzhiyun #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 137*4882a593Smuzhiyun #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) 138*4882a593Smuzhiyun #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 139*4882a593Smuzhiyun #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0) 140*4882a593Smuzhiyun #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 141*4882a593Smuzhiyun #define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4) 142*4882a593Smuzhiyun #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 143*4882a593Smuzhiyun #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8) 144*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc 145*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc) 146*4882a593Smuzhiyun #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 147*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) 148*4882a593Smuzhiyun #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 149*4882a593Smuzhiyun #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) 150*4882a593Smuzhiyun #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec 151*4882a593Smuzhiyun #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* CM2.ALWAYS_ON_CM2 register offsets */ 154*4882a593Smuzhiyun #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 155*4882a593Smuzhiyun #define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000) 156*4882a593Smuzhiyun #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 157*4882a593Smuzhiyun #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020) 158*4882a593Smuzhiyun #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 159*4882a593Smuzhiyun #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028) 160*4882a593Smuzhiyun #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 161*4882a593Smuzhiyun #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030) 162*4882a593Smuzhiyun #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 163*4882a593Smuzhiyun #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038) 164*4882a593Smuzhiyun #define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 165*4882a593Smuzhiyun #define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* CM2.CORE_CM2 register offsets */ 168*4882a593Smuzhiyun #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 169*4882a593Smuzhiyun #define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000) 170*4882a593Smuzhiyun #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 171*4882a593Smuzhiyun #define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008) 172*4882a593Smuzhiyun #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 173*4882a593Smuzhiyun #define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020) 174*4882a593Smuzhiyun #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 175*4882a593Smuzhiyun #define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100) 176*4882a593Smuzhiyun #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 177*4882a593Smuzhiyun #define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108) 178*4882a593Smuzhiyun #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 179*4882a593Smuzhiyun #define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120) 180*4882a593Smuzhiyun #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 181*4882a593Smuzhiyun #define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128) 182*4882a593Smuzhiyun #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 183*4882a593Smuzhiyun #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130) 184*4882a593Smuzhiyun #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 185*4882a593Smuzhiyun #define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200) 186*4882a593Smuzhiyun #define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 187*4882a593Smuzhiyun #define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204) 188*4882a593Smuzhiyun #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 189*4882a593Smuzhiyun #define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208) 190*4882a593Smuzhiyun #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 191*4882a593Smuzhiyun #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220) 192*4882a593Smuzhiyun #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 193*4882a593Smuzhiyun #define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300) 194*4882a593Smuzhiyun #define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 195*4882a593Smuzhiyun #define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304) 196*4882a593Smuzhiyun #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 197*4882a593Smuzhiyun #define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308) 198*4882a593Smuzhiyun #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 199*4882a593Smuzhiyun #define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320) 200*4882a593Smuzhiyun #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 201*4882a593Smuzhiyun #define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400) 202*4882a593Smuzhiyun #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 203*4882a593Smuzhiyun #define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420) 204*4882a593Smuzhiyun #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 205*4882a593Smuzhiyun #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428) 206*4882a593Smuzhiyun #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 207*4882a593Smuzhiyun #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430) 208*4882a593Smuzhiyun #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 209*4882a593Smuzhiyun #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438) 210*4882a593Smuzhiyun #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 211*4882a593Smuzhiyun #define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440) 212*4882a593Smuzhiyun #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 213*4882a593Smuzhiyun #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450) 214*4882a593Smuzhiyun #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 215*4882a593Smuzhiyun #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458) 216*4882a593Smuzhiyun #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 217*4882a593Smuzhiyun #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460) 218*4882a593Smuzhiyun #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 219*4882a593Smuzhiyun #define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500) 220*4882a593Smuzhiyun #define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 221*4882a593Smuzhiyun #define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504) 222*4882a593Smuzhiyun #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 223*4882a593Smuzhiyun #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) 224*4882a593Smuzhiyun #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 225*4882a593Smuzhiyun #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) 226*4882a593Smuzhiyun #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 227*4882a593Smuzhiyun #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) 228*4882a593Smuzhiyun #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 229*4882a593Smuzhiyun #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) 230*4882a593Smuzhiyun #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 231*4882a593Smuzhiyun #define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600) 232*4882a593Smuzhiyun #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 233*4882a593Smuzhiyun #define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608) 234*4882a593Smuzhiyun #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 235*4882a593Smuzhiyun #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620) 236*4882a593Smuzhiyun #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 237*4882a593Smuzhiyun #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628) 238*4882a593Smuzhiyun #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 239*4882a593Smuzhiyun #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630) 240*4882a593Smuzhiyun #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 241*4882a593Smuzhiyun #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638) 242*4882a593Smuzhiyun #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 243*4882a593Smuzhiyun #define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700) 244*4882a593Smuzhiyun #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 245*4882a593Smuzhiyun #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720) 246*4882a593Smuzhiyun #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 247*4882a593Smuzhiyun #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728) 248*4882a593Smuzhiyun #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 249*4882a593Smuzhiyun #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740) 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun /* CM2.IVAHD_CM2 register offsets */ 252*4882a593Smuzhiyun #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 253*4882a593Smuzhiyun #define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000) 254*4882a593Smuzhiyun #define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 255*4882a593Smuzhiyun #define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004) 256*4882a593Smuzhiyun #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 257*4882a593Smuzhiyun #define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008) 258*4882a593Smuzhiyun #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 259*4882a593Smuzhiyun #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020) 260*4882a593Smuzhiyun #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 261*4882a593Smuzhiyun #define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028) 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* CM2.CAM_CM2 register offsets */ 264*4882a593Smuzhiyun #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 265*4882a593Smuzhiyun #define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000) 266*4882a593Smuzhiyun #define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 267*4882a593Smuzhiyun #define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004) 268*4882a593Smuzhiyun #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 269*4882a593Smuzhiyun #define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008) 270*4882a593Smuzhiyun #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 271*4882a593Smuzhiyun #define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020) 272*4882a593Smuzhiyun #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 273*4882a593Smuzhiyun #define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028) 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun /* CM2.DSS_CM2 register offsets */ 276*4882a593Smuzhiyun #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 277*4882a593Smuzhiyun #define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000) 278*4882a593Smuzhiyun #define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 279*4882a593Smuzhiyun #define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004) 280*4882a593Smuzhiyun #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 281*4882a593Smuzhiyun #define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008) 282*4882a593Smuzhiyun #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 283*4882a593Smuzhiyun #define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020) 284*4882a593Smuzhiyun #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 285*4882a593Smuzhiyun #define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028) 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* CM2.GFX_CM2 register offsets */ 288*4882a593Smuzhiyun #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 289*4882a593Smuzhiyun #define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000) 290*4882a593Smuzhiyun #define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 291*4882a593Smuzhiyun #define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004) 292*4882a593Smuzhiyun #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 293*4882a593Smuzhiyun #define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008) 294*4882a593Smuzhiyun #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 295*4882a593Smuzhiyun #define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020) 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun /* CM2.L3INIT_CM2 register offsets */ 298*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 299*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000) 300*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 301*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004) 302*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 303*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008) 304*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 305*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028) 306*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 307*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030) 308*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 309*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038) 310*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 311*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040) 312*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 313*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058) 314*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 315*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060) 316*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 317*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068) 318*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 319*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078) 320*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 321*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080) 322*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 323*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088) 324*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 325*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090) 326*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 327*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098) 328*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 329*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8) 330*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 331*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0) 332*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 333*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8) 334*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 335*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0) 336*4882a593Smuzhiyun #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 337*4882a593Smuzhiyun #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0) 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun /* CM2.L4PER_CM2 register offsets */ 340*4882a593Smuzhiyun #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 341*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000) 342*4882a593Smuzhiyun #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 343*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008) 344*4882a593Smuzhiyun #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 345*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020) 346*4882a593Smuzhiyun #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 347*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028) 348*4882a593Smuzhiyun #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 349*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030) 350*4882a593Smuzhiyun #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 351*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038) 352*4882a593Smuzhiyun #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 353*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040) 354*4882a593Smuzhiyun #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 355*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048) 356*4882a593Smuzhiyun #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 357*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050) 358*4882a593Smuzhiyun #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 359*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058) 360*4882a593Smuzhiyun #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 361*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060) 362*4882a593Smuzhiyun #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 363*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068) 364*4882a593Smuzhiyun #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 365*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070) 366*4882a593Smuzhiyun #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 367*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078) 368*4882a593Smuzhiyun #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 369*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080) 370*4882a593Smuzhiyun #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 371*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088) 372*4882a593Smuzhiyun #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 373*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090) 374*4882a593Smuzhiyun #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 375*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098) 376*4882a593Smuzhiyun #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 377*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0) 378*4882a593Smuzhiyun #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 379*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8) 380*4882a593Smuzhiyun #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 381*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0) 382*4882a593Smuzhiyun #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 383*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8) 384*4882a593Smuzhiyun #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 385*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0) 386*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 387*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0) 388*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 389*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8) 390*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 391*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0) 392*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 393*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8) 394*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 395*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0) 396*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 397*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8) 398*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 399*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100) 400*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 401*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108) 402*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 403*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120) 404*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 405*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128) 406*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 407*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130) 408*4882a593Smuzhiyun #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 409*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138) 410*4882a593Smuzhiyun #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 411*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140) 412*4882a593Smuzhiyun #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 413*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148) 414*4882a593Smuzhiyun #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 415*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150) 416*4882a593Smuzhiyun #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 417*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158) 418*4882a593Smuzhiyun #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 419*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160) 420*4882a593Smuzhiyun #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 421*4882a593Smuzhiyun #define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168) 422*4882a593Smuzhiyun #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 423*4882a593Smuzhiyun #define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180) 424*4882a593Smuzhiyun #define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 425*4882a593Smuzhiyun #define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184) 426*4882a593Smuzhiyun #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 427*4882a593Smuzhiyun #define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188) 428*4882a593Smuzhiyun #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 429*4882a593Smuzhiyun #define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0) 430*4882a593Smuzhiyun #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 431*4882a593Smuzhiyun #define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8) 432*4882a593Smuzhiyun #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 433*4882a593Smuzhiyun #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0) 434*4882a593Smuzhiyun #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 435*4882a593Smuzhiyun #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8) 436*4882a593Smuzhiyun #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 437*4882a593Smuzhiyun #define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0) 438*4882a593Smuzhiyun #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 439*4882a593Smuzhiyun #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8) 440*4882a593Smuzhiyun #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 441*4882a593Smuzhiyun #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8) 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun /* CM2.CEFUSE_CM2 register offsets */ 444*4882a593Smuzhiyun #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 445*4882a593Smuzhiyun #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000) 446*4882a593Smuzhiyun #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 447*4882a593Smuzhiyun #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun #endif 450