1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP54xx CM1 instance offset macros 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Paul Walmsley (paul@pwsan.com) 8*4882a593Smuzhiyun * Rajendra Nayak (rnayak@ti.com) 9*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 12*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 13*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 14*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 15*4882a593Smuzhiyun * up-to-date with the file contents. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H 19*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* CM1 base address */ 22*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \ 25*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg)) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* CM_CORE_AON instances */ 28*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000 29*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100 30*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300 31*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400 32*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500 33*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00 34*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* CM_CORE_AON clockdomain register offsets (from instance start) */ 37*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 38*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000 39*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* CM_CORE_AON */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */ 44*4882a593Smuzhiyun #define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000 45*4882a593Smuzhiyun #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040 46*4882a593Smuzhiyun #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) 47*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080 48*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084 49*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090 50*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094 51*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098 52*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c 53*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0 54*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4 55*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8 56*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac 57*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0 58*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4 59*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8 60*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc 61*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0 62*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4 63*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8 64*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc 65*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0 66*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4 67*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8 68*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc 69*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0 70*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4 71*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8 72*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec 73*4882a593Smuzhiyun #define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */ 76*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000 77*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000) 78*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008 79*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008) 80*4882a593Smuzhiyun #define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010 81*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 82*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020) 83*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 84*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024) 85*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 86*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028) 87*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c 88*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c) 89*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 90*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030) 91*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 92*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034) 93*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038 94*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038) 95*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c 96*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c) 97*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040 98*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040) 99*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044 100*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044) 101*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 102*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c 103*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050 104*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050) 105*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054 106*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054) 107*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058 108*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058) 109*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c 110*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c) 111*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 112*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060) 113*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 114*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064) 115*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 116*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068) 117*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c 118*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c) 119*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 120*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070) 121*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 122*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c 123*4882a593Smuzhiyun #define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 124*4882a593Smuzhiyun #define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c) 125*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 126*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0) 127*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 128*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4) 129*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 130*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8) 131*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac 132*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac) 133*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8 134*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8) 135*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc 136*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc) 137*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 138*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc 139*4882a593Smuzhiyun #define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 140*4882a593Smuzhiyun #define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc) 141*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 142*4882a593Smuzhiyun #define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0) 143*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 144*4882a593Smuzhiyun #define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4) 145*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 146*4882a593Smuzhiyun #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8) 147*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec 148*4882a593Smuzhiyun #define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec) 149*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 150*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0) 151*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 152*4882a593Smuzhiyun #define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4) 153*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 154*4882a593Smuzhiyun #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c 155*4882a593Smuzhiyun #define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 156*4882a593Smuzhiyun #define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 157*4882a593Smuzhiyun #define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 158*4882a593Smuzhiyun #define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */ 161*4882a593Smuzhiyun #define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 162*4882a593Smuzhiyun #define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004 163*4882a593Smuzhiyun #define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008 164*4882a593Smuzhiyun #define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 165*4882a593Smuzhiyun #define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020) 166*4882a593Smuzhiyun #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028 167*4882a593Smuzhiyun #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028) 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* CM_CORE_AON.DSP_CM_CORE_AON register offsets */ 170*4882a593Smuzhiyun #define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000 171*4882a593Smuzhiyun #define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004 172*4882a593Smuzhiyun #define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008 173*4882a593Smuzhiyun #define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020 174*4882a593Smuzhiyun #define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020) 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* CM_CORE_AON.ABE_CM_CORE_AON register offsets */ 177*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000 178*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020 179*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020) 180*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028 181*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028) 182*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030 183*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030) 184*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038 185*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038) 186*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040 187*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040) 188*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 189*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048) 190*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 191*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050) 192*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 193*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058) 194*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060 195*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060) 196*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 197*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068) 198*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 199*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070) 200*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 201*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078) 202*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 203*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080) 204*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088 205*4882a593Smuzhiyun #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088) 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #endif 208