1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP44xx CM1 instance offset macros 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009-2011 Texas Instruments, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2009-2010 Nokia Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Paul Walmsley (paul@pwsan.com) 9*4882a593Smuzhiyun * Rajendra Nayak (rnayak@ti.com) 10*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 13*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 14*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 15*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 16*4882a593Smuzhiyun * up-to-date with the file contents. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 19*4882a593Smuzhiyun * or "OMAP4430". 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 23*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* CM1 base address */ 26*4882a593Smuzhiyun #define OMAP4430_CM1_BASE 0x4a004000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define OMAP44XX_CM1_REGADDR(inst, reg) \ 29*4882a593Smuzhiyun OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg)) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* CM1 instances */ 32*4882a593Smuzhiyun #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000 33*4882a593Smuzhiyun #define OMAP4430_CM1_CKGEN_INST 0x0100 34*4882a593Smuzhiyun #define OMAP4430_CM1_MPU_INST 0x0300 35*4882a593Smuzhiyun #define OMAP4430_CM1_TESLA_INST 0x0400 36*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_INST 0x0500 37*4882a593Smuzhiyun #define OMAP4430_CM1_RESTORE_INST 0x0e00 38*4882a593Smuzhiyun #define OMAP4430_CM1_INSTR_INST 0x0f00 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* CM1 clockdomain register offsets (from instance start) */ 41*4882a593Smuzhiyun #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 42*4882a593Smuzhiyun #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 43*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* CM1 */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* CM1.OCP_SOCKET_CM1 register offsets */ 48*4882a593Smuzhiyun #define OMAP4_REVISION_CM1_OFFSET 0x0000 49*4882a593Smuzhiyun #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) 50*4882a593Smuzhiyun #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 51*4882a593Smuzhiyun #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* CM1.CKGEN_CM1 register offsets */ 54*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 55*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) 56*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 57*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) 58*4882a593Smuzhiyun #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 59*4882a593Smuzhiyun #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) 60*4882a593Smuzhiyun #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 61*4882a593Smuzhiyun #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) 62*4882a593Smuzhiyun #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 63*4882a593Smuzhiyun #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) 64*4882a593Smuzhiyun #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 65*4882a593Smuzhiyun #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) 66*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c 67*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) 68*4882a593Smuzhiyun #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 69*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) 70*4882a593Smuzhiyun #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 71*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) 72*4882a593Smuzhiyun #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 73*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) 74*4882a593Smuzhiyun #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c 75*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) 76*4882a593Smuzhiyun #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 77*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) 78*4882a593Smuzhiyun #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 79*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) 80*4882a593Smuzhiyun #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 81*4882a593Smuzhiyun #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) 82*4882a593Smuzhiyun #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c 83*4882a593Smuzhiyun #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) 84*4882a593Smuzhiyun #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 85*4882a593Smuzhiyun #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) 86*4882a593Smuzhiyun #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 87*4882a593Smuzhiyun #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) 88*4882a593Smuzhiyun #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 89*4882a593Smuzhiyun #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) 90*4882a593Smuzhiyun #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 91*4882a593Smuzhiyun #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) 92*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c 93*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) 94*4882a593Smuzhiyun #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 95*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) 96*4882a593Smuzhiyun #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 97*4882a593Smuzhiyun #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) 98*4882a593Smuzhiyun #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c 99*4882a593Smuzhiyun #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) 100*4882a593Smuzhiyun #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 101*4882a593Smuzhiyun #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) 102*4882a593Smuzhiyun #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 103*4882a593Smuzhiyun #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) 104*4882a593Smuzhiyun #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 105*4882a593Smuzhiyun #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) 106*4882a593Smuzhiyun #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 107*4882a593Smuzhiyun #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) 108*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac 109*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) 110*4882a593Smuzhiyun #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 111*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) 112*4882a593Smuzhiyun #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc 113*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) 114*4882a593Smuzhiyun #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 115*4882a593Smuzhiyun #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) 116*4882a593Smuzhiyun #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc 117*4882a593Smuzhiyun #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) 118*4882a593Smuzhiyun #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 119*4882a593Smuzhiyun #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) 120*4882a593Smuzhiyun #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 121*4882a593Smuzhiyun #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) 122*4882a593Smuzhiyun #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 123*4882a593Smuzhiyun #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) 124*4882a593Smuzhiyun #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 125*4882a593Smuzhiyun #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) 126*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec 127*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) 128*4882a593Smuzhiyun #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 129*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) 130*4882a593Smuzhiyun #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 131*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) 132*4882a593Smuzhiyun #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 133*4882a593Smuzhiyun #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) 134*4882a593Smuzhiyun #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c 135*4882a593Smuzhiyun #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) 136*4882a593Smuzhiyun #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 137*4882a593Smuzhiyun #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) 138*4882a593Smuzhiyun #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 139*4882a593Smuzhiyun #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) 140*4882a593Smuzhiyun #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 141*4882a593Smuzhiyun #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) 142*4882a593Smuzhiyun #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c 143*4882a593Smuzhiyun #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) 144*4882a593Smuzhiyun #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 145*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) 146*4882a593Smuzhiyun #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 147*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) 148*4882a593Smuzhiyun #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c 149*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) 150*4882a593Smuzhiyun #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 151*4882a593Smuzhiyun #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) 152*4882a593Smuzhiyun #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 153*4882a593Smuzhiyun #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) 154*4882a593Smuzhiyun #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c 155*4882a593Smuzhiyun #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) 156*4882a593Smuzhiyun #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 157*4882a593Smuzhiyun #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) 158*4882a593Smuzhiyun #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 159*4882a593Smuzhiyun #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) 160*4882a593Smuzhiyun #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 161*4882a593Smuzhiyun #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) 162*4882a593Smuzhiyun #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 163*4882a593Smuzhiyun #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* CM1.MPU_CM1 register offsets */ 166*4882a593Smuzhiyun #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 167*4882a593Smuzhiyun #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) 168*4882a593Smuzhiyun #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 169*4882a593Smuzhiyun #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) 170*4882a593Smuzhiyun #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 171*4882a593Smuzhiyun #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) 172*4882a593Smuzhiyun #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 173*4882a593Smuzhiyun #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* CM1.TESLA_CM1 register offsets */ 176*4882a593Smuzhiyun #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 177*4882a593Smuzhiyun #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) 178*4882a593Smuzhiyun #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 179*4882a593Smuzhiyun #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) 180*4882a593Smuzhiyun #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 181*4882a593Smuzhiyun #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) 182*4882a593Smuzhiyun #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 183*4882a593Smuzhiyun #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* CM1.ABE_CM1 register offsets */ 186*4882a593Smuzhiyun #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 187*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) 188*4882a593Smuzhiyun #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 189*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) 190*4882a593Smuzhiyun #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 191*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) 192*4882a593Smuzhiyun #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 193*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) 194*4882a593Smuzhiyun #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 195*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) 196*4882a593Smuzhiyun #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 197*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) 198*4882a593Smuzhiyun #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 199*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) 200*4882a593Smuzhiyun #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 201*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) 202*4882a593Smuzhiyun #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 203*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) 204*4882a593Smuzhiyun #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 205*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) 206*4882a593Smuzhiyun #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 207*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) 208*4882a593Smuzhiyun #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 209*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) 210*4882a593Smuzhiyun #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 211*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) 212*4882a593Smuzhiyun #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 213*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) 214*4882a593Smuzhiyun #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 215*4882a593Smuzhiyun #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun #endif 218