1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * DRA7xx Clock Management register bits 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Generated by code originally written by: 8*4882a593Smuzhiyun * Paul Walmsley (paul@pwsan.com) 9*4882a593Smuzhiyun * Rajendra Nayak (rnayak@ti.com) 10*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 13*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 14*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 15*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 16*4882a593Smuzhiyun * up-to-date with the file contents. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H 20*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define DRA7XX_ATL_STATDEP_SHIFT 30 23*4882a593Smuzhiyun #define DRA7XX_CAM_STATDEP_SHIFT 9 24*4882a593Smuzhiyun #define DRA7XX_DSP1_STATDEP_SHIFT 1 25*4882a593Smuzhiyun #define DRA7XX_DSP2_STATDEP_SHIFT 18 26*4882a593Smuzhiyun #define DRA7XX_DSS_STATDEP_SHIFT 8 27*4882a593Smuzhiyun #define DRA7XX_EMIF_STATDEP_SHIFT 4 28*4882a593Smuzhiyun #define DRA7XX_EVE1_STATDEP_SHIFT 19 29*4882a593Smuzhiyun #define DRA7XX_EVE2_STATDEP_SHIFT 20 30*4882a593Smuzhiyun #define DRA7XX_EVE3_STATDEP_SHIFT 21 31*4882a593Smuzhiyun #define DRA7XX_EVE4_STATDEP_SHIFT 22 32*4882a593Smuzhiyun #define DRA7XX_GMAC_STATDEP_SHIFT 25 33*4882a593Smuzhiyun #define DRA7XX_GPU_STATDEP_SHIFT 10 34*4882a593Smuzhiyun #define DRA7XX_IPU1_STATDEP_SHIFT 23 35*4882a593Smuzhiyun #define DRA7XX_IPU2_STATDEP_SHIFT 0 36*4882a593Smuzhiyun #define DRA7XX_IPU_STATDEP_SHIFT 24 37*4882a593Smuzhiyun #define DRA7XX_IVA_STATDEP_SHIFT 2 38*4882a593Smuzhiyun #define DRA7XX_L3INIT_STATDEP_SHIFT 7 39*4882a593Smuzhiyun #define DRA7XX_L3MAIN1_STATDEP_SHIFT 5 40*4882a593Smuzhiyun #define DRA7XX_L4CFG_STATDEP_SHIFT 12 41*4882a593Smuzhiyun #define DRA7XX_L4PER2_STATDEP_SHIFT 26 42*4882a593Smuzhiyun #define DRA7XX_L4PER3_STATDEP_SHIFT 27 43*4882a593Smuzhiyun #define DRA7XX_L4PER_STATDEP_SHIFT 13 44*4882a593Smuzhiyun #define DRA7XX_L4SEC_STATDEP_SHIFT 14 45*4882a593Smuzhiyun #define DRA7XX_PCIE_STATDEP_SHIFT 29 46*4882a593Smuzhiyun #define DRA7XX_VPE_STATDEP_SHIFT 28 47*4882a593Smuzhiyun #define DRA7XX_WKUPAON_STATDEP_SHIFT 15 48*4882a593Smuzhiyun #endif 49