1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP54xx Clock Management register bits 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Paul Walmsley (paul@pwsan.com) 8*4882a593Smuzhiyun * Rajendra Nayak (rnayak@ti.com) 9*4882a593Smuzhiyun * Benoit Cousson (b-cousson@ti.com) 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This file is automatically generated from the OMAP hardware databases. 12*4882a593Smuzhiyun * We respectfully ask that any modifications to this file be coordinated 13*4882a593Smuzhiyun * with the public linux-omap@vger.kernel.org mailing list and the 14*4882a593Smuzhiyun * authors above to ensure that the autogeneration scripts are kept 15*4882a593Smuzhiyun * up-to-date with the file contents. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H 19*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define OMAP54XX_ABE_STATDEP_SHIFT 3 22*4882a593Smuzhiyun #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) 23*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_SHIFT 24 24*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_WIDTH 0x1 25*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_0_0_SHIFT 0 26*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 27*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 28*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 29*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_DIV_SHIFT 25 30*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 31*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_FCLK_SHIFT 24 32*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 33*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 34*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 35*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 36*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 37*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 38*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 39*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_OPP_SHIFT 0 40*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 41*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 42*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 43*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 44*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 45*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 46*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 47*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 48*4882a593Smuzhiyun #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 49*4882a593Smuzhiyun #define OMAP54XX_DIVHS_MASK (0x3f << 0) 50*4882a593Smuzhiyun #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) 51*4882a593Smuzhiyun #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) 52*4882a593Smuzhiyun #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) 53*4882a593Smuzhiyun #define OMAP54XX_DPLL_EN_MASK (0x7 << 0) 54*4882a593Smuzhiyun #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) 55*4882a593Smuzhiyun #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) 56*4882a593Smuzhiyun #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) 57*4882a593Smuzhiyun #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) 58*4882a593Smuzhiyun #define OMAP54XX_DSP_STATDEP_SHIFT 1 59*4882a593Smuzhiyun #define OMAP54XX_DSS_STATDEP_SHIFT 8 60*4882a593Smuzhiyun #define OMAP54XX_EMIF_STATDEP_SHIFT 4 61*4882a593Smuzhiyun #define OMAP54XX_GPU_STATDEP_SHIFT 10 62*4882a593Smuzhiyun #define OMAP54XX_IPU_STATDEP_SHIFT 0 63*4882a593Smuzhiyun #define OMAP54XX_IVA_STATDEP_SHIFT 2 64*4882a593Smuzhiyun #define OMAP54XX_L3INIT_STATDEP_SHIFT 7 65*4882a593Smuzhiyun #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 66*4882a593Smuzhiyun #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 67*4882a593Smuzhiyun #define OMAP54XX_L4CFG_STATDEP_SHIFT 12 68*4882a593Smuzhiyun #define OMAP54XX_L4PER_STATDEP_SHIFT 13 69*4882a593Smuzhiyun #define OMAP54XX_L4SEC_STATDEP_SHIFT 14 70*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 71*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 72*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 73*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 74*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 75*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 76*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 77*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 78*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 79*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 80*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 81*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 82*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 83*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 84*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 85*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 86*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 87*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 88*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 89*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 90*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 91*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 92*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 93*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 94*4882a593Smuzhiyun #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 95*4882a593Smuzhiyun #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 96*4882a593Smuzhiyun #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 97*4882a593Smuzhiyun #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) 98*4882a593Smuzhiyun #define OMAP54XX_SYS_CLKSEL_SHIFT 0 99*4882a593Smuzhiyun #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 100*4882a593Smuzhiyun #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 101*4882a593Smuzhiyun #endif 102