1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 3*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * OMAP3430 Clock Management register bits 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2007-2008 Texas Instruments, Inc. 9*4882a593Smuzhiyun * Copyright (C) 2007-2008 Nokia Corporation 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Written by Paul Walmsley 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) 15*4882a593Smuzhiyun #define OMAP3430_ST_IVA2_SHIFT 0 16*4882a593Smuzhiyun #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 17*4882a593Smuzhiyun #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) 18*4882a593Smuzhiyun #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 19*4882a593Smuzhiyun #define OMAP3430_ST_AES2_SHIFT 28 20*4882a593Smuzhiyun #define OMAP3430_ST_SHA12_SHIFT 27 21*4882a593Smuzhiyun #define AM35XX_ST_UART4_SHIFT 23 22*4882a593Smuzhiyun #define OMAP3430_ST_HDQ_SHIFT 22 23*4882a593Smuzhiyun #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 24*4882a593Smuzhiyun #define OMAP3430_ST_MAILBOXES_SHIFT 7 25*4882a593Smuzhiyun #define OMAP3430_ST_SAD2D_SHIFT 3 26*4882a593Smuzhiyun #define OMAP3430_ST_SDMA_SHIFT 2 27*4882a593Smuzhiyun #define OMAP3430ES2_ST_USBTLL_SHIFT 2 28*4882a593Smuzhiyun #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 29*4882a593Smuzhiyun #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 30*4882a593Smuzhiyun #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 31*4882a593Smuzhiyun #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 32*4882a593Smuzhiyun #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) 33*4882a593Smuzhiyun #define OMAP3430_ST_WDT2_SHIFT 5 34*4882a593Smuzhiyun #define OMAP3430_ST_32KSYNC_SHIFT 2 35*4882a593Smuzhiyun #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 36*4882a593Smuzhiyun #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 37*4882a593Smuzhiyun #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 38*4882a593Smuzhiyun #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 39*4882a593Smuzhiyun #define OMAP3430_ST_MCBSP4_SHIFT 2 40*4882a593Smuzhiyun #define OMAP3430_ST_MCBSP3_SHIFT 1 41*4882a593Smuzhiyun #define OMAP3430_ST_MCBSP2_SHIFT 0 42*4882a593Smuzhiyun #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 43*4882a593Smuzhiyun #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 44*4882a593Smuzhiyun #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 45*4882a593Smuzhiyun #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 46*4882a593Smuzhiyun #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 47*4882a593Smuzhiyun #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 48*4882a593Smuzhiyun #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 49*4882a593Smuzhiyun #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 50*4882a593Smuzhiyun #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 51*4882a593Smuzhiyun #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 52*4882a593Smuzhiyun #endif 53