1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * AM33XX Power Management register bits 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is automatically generated from the AM33XX hardware databases. 5*4882a593Smuzhiyun * Vaibhav Hiremath <hvaibhav@ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 11*4882a593Smuzhiyun * published by the Free Software Foundation version 2. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 14*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty 15*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*4882a593Smuzhiyun * GNU General Public License for more details. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H 21*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define AM33XX_CLKOUT2DIV_SHIFT 3 24*4882a593Smuzhiyun #define AM33XX_CLKOUT2DIV_WIDTH 3 25*4882a593Smuzhiyun #define AM33XX_CLKOUT2EN_SHIFT 7 26*4882a593Smuzhiyun #define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) 27*4882a593Smuzhiyun #define AM33XX_CLKSEL_0_0_SHIFT 0 28*4882a593Smuzhiyun #define AM33XX_CLKSEL_0_0_WIDTH 1 29*4882a593Smuzhiyun #define AM33XX_CLKSEL_0_0_MASK (1 << 0) 30*4882a593Smuzhiyun #define AM33XX_CLKSEL_0_1_MASK (3 << 0) 31*4882a593Smuzhiyun #define AM33XX_CLKSEL_0_2_MASK (7 << 0) 32*4882a593Smuzhiyun #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) 33*4882a593Smuzhiyun #define AM33XX_CLKTRCTRL_SHIFT 0 34*4882a593Smuzhiyun #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) 35*4882a593Smuzhiyun #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 36*4882a593Smuzhiyun #define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 37*4882a593Smuzhiyun #define AM33XX_DPLL_DIV_MASK (0x7f << 0) 38*4882a593Smuzhiyun #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) 39*4882a593Smuzhiyun #define AM33XX_DPLL_EN_MASK (0x7 << 0) 40*4882a593Smuzhiyun #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) 41*4882a593Smuzhiyun #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) 42*4882a593Smuzhiyun #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 43*4882a593Smuzhiyun #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 44*4882a593Smuzhiyun #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 45*4882a593Smuzhiyun #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 46*4882a593Smuzhiyun #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 47*4882a593Smuzhiyun #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 48*4882a593Smuzhiyun #define AM33XX_IDLEST_SHIFT 16 49*4882a593Smuzhiyun #define AM33XX_IDLEST_MASK (0x3 << 16) 50*4882a593Smuzhiyun #define AM33XX_MODULEMODE_SHIFT 0 51*4882a593Smuzhiyun #define AM33XX_MODULEMODE_MASK (0x3 << 0) 52*4882a593Smuzhiyun #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 53*4882a593Smuzhiyun #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 54*4882a593Smuzhiyun #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 55*4882a593Smuzhiyun #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 56*4882a593Smuzhiyun #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 57*4882a593Smuzhiyun #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 58*4882a593Smuzhiyun #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 59*4882a593Smuzhiyun #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 60*4882a593Smuzhiyun #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 61*4882a593Smuzhiyun #define AM33XX_STM_PMD_CLKSEL_WIDTH 2 62*4882a593Smuzhiyun #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) 63*4882a593Smuzhiyun #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 64*4882a593Smuzhiyun #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 65*4882a593Smuzhiyun #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 66*4882a593Smuzhiyun #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 67*4882a593Smuzhiyun #define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 68*4882a593Smuzhiyun #endif 69