1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H 3*4882a593Smuzhiyun #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * OMAP24XX Clock Management register bits 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2007 Texas Instruments, Inc. 9*4882a593Smuzhiyun * Copyright (C) 2007 Nokia Corporation 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Written by Paul Walmsley 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) 15*4882a593Smuzhiyun #define OMAP24XX_EN_DSS1_MASK (1 << 0) 16*4882a593Smuzhiyun #define OMAP24XX_ST_MAILBOXES_SHIFT 30 17*4882a593Smuzhiyun #define OMAP24XX_ST_HDQ_SHIFT 23 18*4882a593Smuzhiyun #define OMAP2420_ST_I2C2_SHIFT 20 19*4882a593Smuzhiyun #define OMAP2430_ST_I2CHS1_SHIFT 19 20*4882a593Smuzhiyun #define OMAP2420_ST_I2C1_SHIFT 19 21*4882a593Smuzhiyun #define OMAP2430_ST_I2CHS2_SHIFT 20 22*4882a593Smuzhiyun #define OMAP24XX_ST_MCBSP2_SHIFT 16 23*4882a593Smuzhiyun #define OMAP24XX_ST_MCBSP1_SHIFT 15 24*4882a593Smuzhiyun #define OMAP2430_ST_MCBSP5_SHIFT 5 25*4882a593Smuzhiyun #define OMAP2430_ST_MCBSP4_SHIFT 4 26*4882a593Smuzhiyun #define OMAP2430_ST_MCBSP3_SHIFT 3 27*4882a593Smuzhiyun #define OMAP24XX_ST_AES_SHIFT 3 28*4882a593Smuzhiyun #define OMAP24XX_ST_RNG_SHIFT 2 29*4882a593Smuzhiyun #define OMAP24XX_ST_SHA_SHIFT 1 30*4882a593Smuzhiyun #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) 31*4882a593Smuzhiyun #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) 32*4882a593Smuzhiyun #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) 33*4882a593Smuzhiyun #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) 34*4882a593Smuzhiyun #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) 35*4882a593Smuzhiyun #define OMAP24XX_ST_MPU_WDT_SHIFT 3 36*4882a593Smuzhiyun #define OMAP24XX_ST_32KSYNC_SHIFT 1 37*4882a593Smuzhiyun #define OMAP24XX_EN_54M_PLL_SHIFT 6 38*4882a593Smuzhiyun #define OMAP24XX_EN_96M_PLL_SHIFT 2 39*4882a593Smuzhiyun #define OMAP24XX_ST_54M_APLL_SHIFT 9 40*4882a593Smuzhiyun #define OMAP24XX_ST_96M_APLL_SHIFT 8 41*4882a593Smuzhiyun #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) 42*4882a593Smuzhiyun #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) 43*4882a593Smuzhiyun #define OMAP24XX_AUTO_DPLL_SHIFT 0 44*4882a593Smuzhiyun #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) 45*4882a593Smuzhiyun #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) 46*4882a593Smuzhiyun #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) 47*4882a593Smuzhiyun #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) 48*4882a593Smuzhiyun #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) 49*4882a593Smuzhiyun #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 50*4882a593Smuzhiyun #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 51*4882a593Smuzhiyun #endif 52