1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * OMAP2420 clockdomains
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2008-2011 Texas Instruments, Inc.
6*4882a593Smuzhiyun * Copyright (C) 2008-2010 Nokia Corporation
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Paul Walmsley, Jouni Högander
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This file contains clockdomains and clockdomain wakeup dependencies
11*4882a593Smuzhiyun * for OMAP2420 chips. Some notes:
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * A useful validation rule for struct clockdomain: Any clockdomain
14*4882a593Smuzhiyun * referenced by a wkdep_srcs must have a dep_bit assigned. So
15*4882a593Smuzhiyun * wkdep_srcs are really just software-controllable dependencies.
16*4882a593Smuzhiyun * Non-software-controllable dependencies do exist, but they are not
17*4882a593Smuzhiyun * encoded below (yet).
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * 24xx does not support programmable sleep dependencies (SLEEPDEP)
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * The overly-specific dep_bit names are due to a bit name collision
22*4882a593Smuzhiyun * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
23*4882a593Smuzhiyun * value are the same for all powerdomains: 2
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
26*4882a593Smuzhiyun * sanity check?
27*4882a593Smuzhiyun * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * To-Do List
32*4882a593Smuzhiyun * -> Port the Sleep/Wakeup dependencies for the domains
33*4882a593Smuzhiyun * from the Power domain framework
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #include <linux/kernel.h>
37*4882a593Smuzhiyun #include <linux/io.h>
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #include "soc.h"
40*4882a593Smuzhiyun #include "clockdomain.h"
41*4882a593Smuzhiyun #include "prm2xxx_3xxx.h"
42*4882a593Smuzhiyun #include "cm2xxx_3xxx.h"
43*4882a593Smuzhiyun #include "cm-regbits-24xx.h"
44*4882a593Smuzhiyun #include "prm-regbits-24xx.h"
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * Clockdomain dependencies for wkdeps
48*4882a593Smuzhiyun *
49*4882a593Smuzhiyun * XXX Hardware dependencies (e.g., dependencies that cannot be
50*4882a593Smuzhiyun * changed in software) are not included here yet, but should be.
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Wakeup dependency source arrays */
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* 2420-specific possible wakeup dependencies */
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
58*4882a593Smuzhiyun static struct clkdm_dep mpu_2420_wkdeps[] = {
59*4882a593Smuzhiyun { .clkdm_name = "core_l3_clkdm" },
60*4882a593Smuzhiyun { .clkdm_name = "core_l4_clkdm" },
61*4882a593Smuzhiyun { .clkdm_name = "dsp_clkdm" },
62*4882a593Smuzhiyun { .clkdm_name = "wkup_clkdm" },
63*4882a593Smuzhiyun { NULL },
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
67*4882a593Smuzhiyun static struct clkdm_dep core_2420_wkdeps[] = {
68*4882a593Smuzhiyun { .clkdm_name = "dsp_clkdm" },
69*4882a593Smuzhiyun { .clkdm_name = "gfx_clkdm" },
70*4882a593Smuzhiyun { .clkdm_name = "mpu_clkdm" },
71*4882a593Smuzhiyun { .clkdm_name = "wkup_clkdm" },
72*4882a593Smuzhiyun { NULL },
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun * 2420-only clockdomains
77*4882a593Smuzhiyun */
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static struct clockdomain mpu_2420_clkdm = {
80*4882a593Smuzhiyun .name = "mpu_clkdm",
81*4882a593Smuzhiyun .pwrdm = { .name = "mpu_pwrdm" },
82*4882a593Smuzhiyun .flags = CLKDM_CAN_HWSUP,
83*4882a593Smuzhiyun .wkdep_srcs = mpu_2420_wkdeps,
84*4882a593Smuzhiyun .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static struct clockdomain iva1_2420_clkdm = {
88*4882a593Smuzhiyun .name = "iva1_clkdm",
89*4882a593Smuzhiyun .pwrdm = { .name = "dsp_pwrdm" },
90*4882a593Smuzhiyun .flags = CLKDM_CAN_HWSUP_SWSUP,
91*4882a593Smuzhiyun .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
92*4882a593Smuzhiyun .wkdep_srcs = dsp_24xx_wkdeps,
93*4882a593Smuzhiyun .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static struct clockdomain dsp_2420_clkdm = {
97*4882a593Smuzhiyun .name = "dsp_clkdm",
98*4882a593Smuzhiyun .pwrdm = { .name = "dsp_pwrdm" },
99*4882a593Smuzhiyun .flags = CLKDM_CAN_HWSUP_SWSUP,
100*4882a593Smuzhiyun .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static struct clockdomain gfx_2420_clkdm = {
104*4882a593Smuzhiyun .name = "gfx_clkdm",
105*4882a593Smuzhiyun .pwrdm = { .name = "gfx_pwrdm" },
106*4882a593Smuzhiyun .flags = CLKDM_CAN_HWSUP_SWSUP,
107*4882a593Smuzhiyun .wkdep_srcs = gfx_24xx_wkdeps,
108*4882a593Smuzhiyun .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun static struct clockdomain core_l3_2420_clkdm = {
112*4882a593Smuzhiyun .name = "core_l3_clkdm",
113*4882a593Smuzhiyun .pwrdm = { .name = "core_pwrdm" },
114*4882a593Smuzhiyun .flags = CLKDM_CAN_HWSUP,
115*4882a593Smuzhiyun .wkdep_srcs = core_2420_wkdeps,
116*4882a593Smuzhiyun .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun static struct clockdomain core_l4_2420_clkdm = {
120*4882a593Smuzhiyun .name = "core_l4_clkdm",
121*4882a593Smuzhiyun .pwrdm = { .name = "core_pwrdm" },
122*4882a593Smuzhiyun .flags = CLKDM_CAN_HWSUP,
123*4882a593Smuzhiyun .wkdep_srcs = core_2420_wkdeps,
124*4882a593Smuzhiyun .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun static struct clockdomain dss_2420_clkdm = {
128*4882a593Smuzhiyun .name = "dss_clkdm",
129*4882a593Smuzhiyun .pwrdm = { .name = "core_pwrdm" },
130*4882a593Smuzhiyun .flags = CLKDM_CAN_HWSUP,
131*4882a593Smuzhiyun .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun static struct clockdomain *clockdomains_omap242x[] __initdata = {
135*4882a593Smuzhiyun &wkup_common_clkdm,
136*4882a593Smuzhiyun &mpu_2420_clkdm,
137*4882a593Smuzhiyun &iva1_2420_clkdm,
138*4882a593Smuzhiyun &dsp_2420_clkdm,
139*4882a593Smuzhiyun &gfx_2420_clkdm,
140*4882a593Smuzhiyun &core_l3_2420_clkdm,
141*4882a593Smuzhiyun &core_l4_2420_clkdm,
142*4882a593Smuzhiyun &dss_2420_clkdm,
143*4882a593Smuzhiyun NULL,
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun
omap242x_clockdomains_init(void)146*4882a593Smuzhiyun void __init omap242x_clockdomains_init(void)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun if (!cpu_is_omap242x())
149*4882a593Smuzhiyun return;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun clkdm_register_platform_funcs(&omap2_clkdm_operations);
152*4882a593Smuzhiyun clkdm_register_clkdms(clockdomains_omap242x);
153*4882a593Smuzhiyun clkdm_complete_init();
154*4882a593Smuzhiyun }
155