1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP2-specific DPLL control functions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Nokia Corporation 6*4882a593Smuzhiyun * Paul Walmsley 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/kernel.h> 10*4882a593Smuzhiyun #include <linux/errno.h> 11*4882a593Smuzhiyun #include <linux/clk.h> 12*4882a593Smuzhiyun #include <linux/io.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include "clock.h" 15*4882a593Smuzhiyun #include "cm2xxx.h" 16*4882a593Smuzhiyun #include "cm-regbits-24xx.h" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Private functions */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /** 21*4882a593Smuzhiyun * _allow_idle - enable DPLL autoidle bits 22*4882a593Smuzhiyun * @clk: struct clk * of the DPLL to operate on 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Enable DPLL automatic idle control. The DPLL will enter low-power 25*4882a593Smuzhiyun * stop when its downstream clocks are gated. No return value. 26*4882a593Smuzhiyun * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 27*4882a593Smuzhiyun * instead. Add some mechanism to optionally enter this mode. 28*4882a593Smuzhiyun */ _allow_idle(struct clk_hw_omap * clk)29*4882a593Smuzhiyunstatic void _allow_idle(struct clk_hw_omap *clk) 30*4882a593Smuzhiyun { 31*4882a593Smuzhiyun if (!clk || !clk->dpll_data) 32*4882a593Smuzhiyun return; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun omap2xxx_cm_set_dpll_auto_low_power_stop(); 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /** 38*4882a593Smuzhiyun * _deny_idle - prevent DPLL from automatically idling 39*4882a593Smuzhiyun * @clk: struct clk * of the DPLL to operate on 40*4882a593Smuzhiyun * 41*4882a593Smuzhiyun * Disable DPLL automatic idle control. No return value. 42*4882a593Smuzhiyun */ _deny_idle(struct clk_hw_omap * clk)43*4882a593Smuzhiyunstatic void _deny_idle(struct clk_hw_omap *clk) 44*4882a593Smuzhiyun { 45*4882a593Smuzhiyun if (!clk || !clk->dpll_data) 46*4882a593Smuzhiyun return; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun omap2xxx_cm_set_dpll_disable_autoidle(); 49*4882a593Smuzhiyun } 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Public data */ 53*4882a593Smuzhiyun const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = { 54*4882a593Smuzhiyun .allow_idle = _allow_idle, 55*4882a593Smuzhiyun .deny_idle = _deny_idle, 56*4882a593Smuzhiyun }; 57