1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OMAP1 reset support 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #include <linux/kernel.h> 6*4882a593Smuzhiyun #include <linux/io.h> 7*4882a593Smuzhiyun #include <linux/reboot.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <mach/hardware.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "iomap.h" 12*4882a593Smuzhiyun #include "common.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* ARM_SYSST bit shifts related to SoC reset sources */ 15*4882a593Smuzhiyun #define ARM_SYSST_POR_SHIFT 5 16*4882a593Smuzhiyun #define ARM_SYSST_EXT_RST_SHIFT 4 17*4882a593Smuzhiyun #define ARM_SYSST_ARM_WDRST_SHIFT 2 18*4882a593Smuzhiyun #define ARM_SYSST_GLOB_SWRST_SHIFT 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Standardized reset source bits (across all OMAP SoCs) */ 21*4882a593Smuzhiyun #define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0 22*4882a593Smuzhiyun #define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1 23*4882a593Smuzhiyun #define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3 24*4882a593Smuzhiyun #define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun omap1_restart(enum reboot_mode mode,const char * cmd)27*4882a593Smuzhiyunvoid omap1_restart(enum reboot_mode mode, const char *cmd) 28*4882a593Smuzhiyun { 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 31*4882a593Smuzhiyun * "Global Software Reset Affects Traffic Controller Frequency". 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun if (cpu_is_omap5912()) { 34*4882a593Smuzhiyun omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); 35*4882a593Smuzhiyun omap_writew(0x8, ARM_RSTCT1); 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun omap_writew(1, ARM_RSTCT1); 39*4882a593Smuzhiyun } 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /** 42*4882a593Smuzhiyun * omap1_get_reset_sources - return the source of the SoC's last reset 43*4882a593Smuzhiyun * 44*4882a593Smuzhiyun * Returns bits that represent the last reset source for the SoC. The 45*4882a593Smuzhiyun * format is standardized across OMAPs for use by the OMAP watchdog. 46*4882a593Smuzhiyun */ omap1_get_reset_sources(void)47*4882a593Smuzhiyunu32 omap1_get_reset_sources(void) 48*4882a593Smuzhiyun { 49*4882a593Smuzhiyun u32 ret = 0; 50*4882a593Smuzhiyun u16 rs; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun rs = __raw_readw(OMAP1_IO_ADDRESS(ARM_SYSST)); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun if (rs & (1 << ARM_SYSST_POR_SHIFT)) 55*4882a593Smuzhiyun ret |= 1 << OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT; 56*4882a593Smuzhiyun if (rs & (1 << ARM_SYSST_EXT_RST_SHIFT)) 57*4882a593Smuzhiyun ret |= 1 << OMAP_EXTWARM_RST_SRC_ID_SHIFT; 58*4882a593Smuzhiyun if (rs & (1 << ARM_SYSST_ARM_WDRST_SHIFT)) 59*4882a593Smuzhiyun ret |= 1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT; 60*4882a593Smuzhiyun if (rs & (1 << ARM_SYSST_GLOB_SWRST_SHIFT)) 61*4882a593Smuzhiyun ret |= 1 << OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun return ret; 64*4882a593Smuzhiyun } 65