1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Hardware definitions for TI OMAP1610/5912/1710 processors. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 7*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the 8*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your 9*4882a593Smuzhiyun * option) any later version. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 12*4882a593Smuzhiyun * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 14*4882a593Smuzhiyun * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 15*4882a593Smuzhiyun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16*4882a593Smuzhiyun * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 17*4882a593Smuzhiyun * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 18*4882a593Smuzhiyun * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 19*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 20*4882a593Smuzhiyun * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along 23*4882a593Smuzhiyun * with this program; if not, write to the Free Software Foundation, Inc., 24*4882a593Smuzhiyun * 675 Mass Ave, Cambridge, MA 02139, USA. 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifndef __ASM_ARCH_OMAP16XX_H 28*4882a593Smuzhiyun #define __ASM_ARCH_OMAP16XX_H 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 32*4882a593Smuzhiyun * Base addresses 33*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define OMAP16XX_DSP_BASE 0xE0000000 39*4882a593Smuzhiyun #define OMAP16XX_DSP_SIZE 0x28000 40*4882a593Smuzhiyun #define OMAP16XX_DSP_START 0xE0000000 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define OMAP16XX_DSPREG_BASE 0xE1000000 43*4882a593Smuzhiyun #define OMAP16XX_DSPREG_SIZE SZ_128K 44*4882a593Smuzhiyun #define OMAP16XX_DSPREG_START 0xE1000000 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define OMAP16XX_SEC_BASE 0xFFFE4000 47*4882a593Smuzhiyun #define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000) 48*4882a593Smuzhiyun #define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800) 49*4882a593Smuzhiyun #define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * --------------------------------------------------------------------------- 53*4882a593Smuzhiyun * Interrupts 54*4882a593Smuzhiyun * --------------------------------------------------------------------------- 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun #define OMAP_IH2_0_BASE (0xfffe0000) 57*4882a593Smuzhiyun #define OMAP_IH2_1_BASE (0xfffe0100) 58*4882a593Smuzhiyun #define OMAP_IH2_2_BASE (0xfffe0200) 59*4882a593Smuzhiyun #define OMAP_IH2_3_BASE (0xfffe0300) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00) 62*4882a593Smuzhiyun #define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04) 63*4882a593Smuzhiyun #define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10) 64*4882a593Smuzhiyun #define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14) 65*4882a593Smuzhiyun #define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18) 66*4882a593Smuzhiyun #define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c) 67*4882a593Smuzhiyun #define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00) 70*4882a593Smuzhiyun #define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04) 71*4882a593Smuzhiyun #define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10) 72*4882a593Smuzhiyun #define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14) 73*4882a593Smuzhiyun #define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18) 74*4882a593Smuzhiyun #define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c) 75*4882a593Smuzhiyun #define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00) 78*4882a593Smuzhiyun #define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04) 79*4882a593Smuzhiyun #define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10) 80*4882a593Smuzhiyun #define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14) 81*4882a593Smuzhiyun #define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18) 82*4882a593Smuzhiyun #define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c) 83*4882a593Smuzhiyun #define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00) 86*4882a593Smuzhiyun #define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04) 87*4882a593Smuzhiyun #define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10) 88*4882a593Smuzhiyun #define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14) 89*4882a593Smuzhiyun #define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18) 90*4882a593Smuzhiyun #define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c) 91*4882a593Smuzhiyun #define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* 94*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 95*4882a593Smuzhiyun * Clocks 96*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun #define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 102*4882a593Smuzhiyun * Pin configuration registers 103*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun #define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8) 106*4882a593Smuzhiyun #define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9) 107*4882a593Smuzhiyun #define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10) 108*4882a593Smuzhiyun #define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11) 109*4882a593Smuzhiyun #define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* 112*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 113*4882a593Smuzhiyun * System control registers 114*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun #define OMAP1610_RESET_CONTROL 0xfffe1140 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* 119*4882a593Smuzhiyun * --------------------------------------------------------------------------- 120*4882a593Smuzhiyun * TIPB bus interface 121*4882a593Smuzhiyun * --------------------------------------------------------------------------- 122*4882a593Smuzhiyun */ 123*4882a593Smuzhiyun #define TIPB_SWITCH_BASE (0xfffbc800) 124*4882a593Smuzhiyun #define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* UART3 Registers Mapping through MPU bus */ 127*4882a593Smuzhiyun #define UART3_RHR (OMAP1_UART3_BASE + 0) 128*4882a593Smuzhiyun #define UART3_THR (OMAP1_UART3_BASE + 0) 129*4882a593Smuzhiyun #define UART3_DLL (OMAP1_UART3_BASE + 0) 130*4882a593Smuzhiyun #define UART3_IER (OMAP1_UART3_BASE + 4) 131*4882a593Smuzhiyun #define UART3_DLH (OMAP1_UART3_BASE + 4) 132*4882a593Smuzhiyun #define UART3_IIR (OMAP1_UART3_BASE + 8) 133*4882a593Smuzhiyun #define UART3_FCR (OMAP1_UART3_BASE + 8) 134*4882a593Smuzhiyun #define UART3_EFR (OMAP1_UART3_BASE + 8) 135*4882a593Smuzhiyun #define UART3_LCR (OMAP1_UART3_BASE + 0x0C) 136*4882a593Smuzhiyun #define UART3_MCR (OMAP1_UART3_BASE + 0x10) 137*4882a593Smuzhiyun #define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10) 138*4882a593Smuzhiyun #define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14) 139*4882a593Smuzhiyun #define UART3_LSR (OMAP1_UART3_BASE + 0x14) 140*4882a593Smuzhiyun #define UART3_TCR (OMAP1_UART3_BASE + 0x18) 141*4882a593Smuzhiyun #define UART3_MSR (OMAP1_UART3_BASE + 0x18) 142*4882a593Smuzhiyun #define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18) 143*4882a593Smuzhiyun #define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C) 144*4882a593Smuzhiyun #define UART3_SPR (OMAP1_UART3_BASE + 0x1C) 145*4882a593Smuzhiyun #define UART3_TLR (OMAP1_UART3_BASE + 0x1C) 146*4882a593Smuzhiyun #define UART3_MDR1 (OMAP1_UART3_BASE + 0x20) 147*4882a593Smuzhiyun #define UART3_MDR2 (OMAP1_UART3_BASE + 0x24) 148*4882a593Smuzhiyun #define UART3_SFLSR (OMAP1_UART3_BASE + 0x28) 149*4882a593Smuzhiyun #define UART3_TXFLL (OMAP1_UART3_BASE + 0x28) 150*4882a593Smuzhiyun #define UART3_RESUME (OMAP1_UART3_BASE + 0x2C) 151*4882a593Smuzhiyun #define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C) 152*4882a593Smuzhiyun #define UART3_SFREGL (OMAP1_UART3_BASE + 0x30) 153*4882a593Smuzhiyun #define UART3_RXFLL (OMAP1_UART3_BASE + 0x30) 154*4882a593Smuzhiyun #define UART3_SFREGH (OMAP1_UART3_BASE + 0x34) 155*4882a593Smuzhiyun #define UART3_RXFLH (OMAP1_UART3_BASE + 0x34) 156*4882a593Smuzhiyun #define UART3_BLR (OMAP1_UART3_BASE + 0x38) 157*4882a593Smuzhiyun #define UART3_ACREG (OMAP1_UART3_BASE + 0x3C) 158*4882a593Smuzhiyun #define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C) 159*4882a593Smuzhiyun #define UART3_SCR (OMAP1_UART3_BASE + 0x40) 160*4882a593Smuzhiyun #define UART3_SSR (OMAP1_UART3_BASE + 0x44) 161*4882a593Smuzhiyun #define UART3_EBLR (OMAP1_UART3_BASE + 0x48) 162*4882a593Smuzhiyun #define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C) 163*4882a593Smuzhiyun #define UART3_MVR (OMAP1_UART3_BASE + 0x50) 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* 166*4882a593Smuzhiyun * --------------------------------------------------------------------------- 167*4882a593Smuzhiyun * Watchdog timer 168*4882a593Smuzhiyun * --------------------------------------------------------------------------- 169*4882a593Smuzhiyun */ 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* 32-bit Watchdog timer in OMAP 16XX */ 172*4882a593Smuzhiyun #define OMAP_16XX_WATCHDOG_BASE (0xfffeb000) 173*4882a593Smuzhiyun #define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00) 174*4882a593Smuzhiyun #define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10) 175*4882a593Smuzhiyun #define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14) 176*4882a593Smuzhiyun #define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24) 177*4882a593Smuzhiyun #define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28) 178*4882a593Smuzhiyun #define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c) 179*4882a593Smuzhiyun #define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30) 180*4882a593Smuzhiyun #define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34) 181*4882a593Smuzhiyun #define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48) 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define WCLR_PRE_SHIFT 5 184*4882a593Smuzhiyun #define WCLR_PTV_SHIFT 2 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define WWPS_W_PEND_WSPR (1 << 4) 187*4882a593Smuzhiyun #define WWPS_W_PEND_WTGR (1 << 3) 188*4882a593Smuzhiyun #define WWPS_W_PEND_WLDR (1 << 2) 189*4882a593Smuzhiyun #define WWPS_W_PEND_WCRR (1 << 1) 190*4882a593Smuzhiyun #define WWPS_W_PEND_WCLR (1 << 0) 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define WSPR_ENABLE_0 (0x0000bbbb) 193*4882a593Smuzhiyun #define WSPR_ENABLE_1 (0x00004444) 194*4882a593Smuzhiyun #define WSPR_DISABLE_0 (0x0000aaaa) 195*4882a593Smuzhiyun #define WSPR_DISABLE_1 (0x00005555) 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun #define OMAP16XX_DSP_MMU_BASE (0xfffed200) 198*4882a593Smuzhiyun #define OMAP16XX_MAILBOX_BASE (0xfffcf000) 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #endif /* __ASM_ARCH_OMAP16XX_H */ 201*4882a593Smuzhiyun 202