1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Hardware definitions for TI OMAP1510 processor. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 7*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the 8*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your 9*4882a593Smuzhiyun * option) any later version. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 12*4882a593Smuzhiyun * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 14*4882a593Smuzhiyun * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 15*4882a593Smuzhiyun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16*4882a593Smuzhiyun * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 17*4882a593Smuzhiyun * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 18*4882a593Smuzhiyun * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 19*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 20*4882a593Smuzhiyun * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along 23*4882a593Smuzhiyun * with this program; if not, write to the Free Software Foundation, Inc., 24*4882a593Smuzhiyun * 675 Mass Ave, Cambridge, MA 02139, USA. 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifndef __ASM_ARCH_OMAP15XX_H 28*4882a593Smuzhiyun #define __ASM_ARCH_OMAP15XX_H 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 32*4882a593Smuzhiyun * Base addresses 33*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define OMAP1510_DSP_BASE 0xE0000000 39*4882a593Smuzhiyun #define OMAP1510_DSP_SIZE 0x28000 40*4882a593Smuzhiyun #define OMAP1510_DSP_START 0xE0000000 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define OMAP1510_DSPREG_BASE 0xE1000000 43*4882a593Smuzhiyun #define OMAP1510_DSPREG_SIZE SZ_128K 44*4882a593Smuzhiyun #define OMAP1510_DSPREG_START 0xE1000000 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define OMAP1510_DSP_MMU_BASE (0xfffed200) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * --------------------------------------------------------------------------- 50*4882a593Smuzhiyun * OMAP-1510 FPGA 51*4882a593Smuzhiyun * --------------------------------------------------------------------------- 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun #define OMAP1510_FPGA_BASE 0xE8000000 /* VA */ 54*4882a593Smuzhiyun #define OMAP1510_FPGA_SIZE SZ_4K 55*4882a593Smuzhiyun #define OMAP1510_FPGA_START 0x08000000 /* PA */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Revision */ 58*4882a593Smuzhiyun #define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0) 59*4882a593Smuzhiyun #define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1) 60*4882a593Smuzhiyun #define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2) 61*4882a593Smuzhiyun #define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3) 62*4882a593Smuzhiyun #define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4) 63*4882a593Smuzhiyun #define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Interrupt status */ 66*4882a593Smuzhiyun #define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6) 67*4882a593Smuzhiyun #define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Interrupt mask */ 70*4882a593Smuzhiyun #define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8) 71*4882a593Smuzhiyun #define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Reset registers */ 74*4882a593Smuzhiyun #define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa) 75*4882a593Smuzhiyun #define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc) 78*4882a593Smuzhiyun #define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe) 79*4882a593Smuzhiyun #define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf) 80*4882a593Smuzhiyun #define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14) 81*4882a593Smuzhiyun #define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15) 82*4882a593Smuzhiyun #define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16) 83*4882a593Smuzhiyun #define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18) 84*4882a593Smuzhiyun #define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c) 85*4882a593Smuzhiyun #define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100) 86*4882a593Smuzhiyun #define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101) 87*4882a593Smuzhiyun #define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205) 92*4882a593Smuzhiyun #define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206) 93*4882a593Smuzhiyun #define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207) 94*4882a593Smuzhiyun #define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208) 95*4882a593Smuzhiyun #define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209) 96*4882a593Smuzhiyun #define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a) 97*4882a593Smuzhiyun #define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b) 98*4882a593Smuzhiyun #define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d) 99*4882a593Smuzhiyun #define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e) 100*4882a593Smuzhiyun #define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * Power up Giga UART driver, turn on HID clock. 106*4882a593Smuzhiyun * Turn off BT power, since we're not using it and it 107*4882a593Smuzhiyun * draws power. 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun #define OMAP1510_FPGA_RESET_VALUE 0x42 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) 112*4882a593Smuzhiyun #define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) 113*4882a593Smuzhiyun #define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) 114*4882a593Smuzhiyun #define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) 115*4882a593Smuzhiyun #define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) 116*4882a593Smuzhiyun #define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) 117*4882a593Smuzhiyun #define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) 118*4882a593Smuzhiyun #define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* 121*4882a593Smuzhiyun * Innovator/OMAP1510 FPGA HID register bit definitions 122*4882a593Smuzhiyun */ 123*4882a593Smuzhiyun #define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */ 124*4882a593Smuzhiyun #define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */ 125*4882a593Smuzhiyun #define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ 126*4882a593Smuzhiyun #define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ 127*4882a593Smuzhiyun #define OMAP1510_FPGA_HID_MISO (1<<4) /* input */ 128*4882a593Smuzhiyun #define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ 129*4882a593Smuzhiyun #define OMAP1510_FPGA_HID_rsrvd (1<<6) 130*4882a593Smuzhiyun #define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* The FPGA IRQ is cascaded through GPIO_13 */ 133*4882a593Smuzhiyun #define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* IRQ Numbers for interrupts muxed through the FPGA */ 136*4882a593Smuzhiyun #define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0) 137*4882a593Smuzhiyun #define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1) 138*4882a593Smuzhiyun #define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2) 139*4882a593Smuzhiyun #define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3) 140*4882a593Smuzhiyun #define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4) 141*4882a593Smuzhiyun #define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5) 142*4882a593Smuzhiyun #define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6) 143*4882a593Smuzhiyun #define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7) 144*4882a593Smuzhiyun #define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8) 145*4882a593Smuzhiyun #define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9) 146*4882a593Smuzhiyun #define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10) 147*4882a593Smuzhiyun #define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11) 148*4882a593Smuzhiyun #define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12) 149*4882a593Smuzhiyun #define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13) 150*4882a593Smuzhiyun #define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14) 151*4882a593Smuzhiyun #define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15) 152*4882a593Smuzhiyun #define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16) 153*4882a593Smuzhiyun #define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17) 154*4882a593Smuzhiyun #define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18) 155*4882a593Smuzhiyun #define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19) 156*4882a593Smuzhiyun #define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20) 157*4882a593Smuzhiyun #define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21) 158*4882a593Smuzhiyun #define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22) 159*4882a593Smuzhiyun #define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #endif /* __ASM_ARCH_OMAP15XX_H */ 162*4882a593Smuzhiyun 163