1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-omap1/include/mach/lcd_dma.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Extracted from arch/arm/plat-omap/include/plat/dma.h 6*4882a593Smuzhiyun * Copyright (C) 2003 Nokia Corporation 7*4882a593Smuzhiyun * Author: Juha Yrjölä <juha.yrjola@nokia.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __MACH_OMAP1_LCD_DMA_H__ 10*4882a593Smuzhiyun #define __MACH_OMAP1_LCD_DMA_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Hardware registers for LCD DMA */ 13*4882a593Smuzhiyun #define OMAP1510_DMA_LCD_BASE (0xfffedb00) 14*4882a593Smuzhiyun #define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00) 15*4882a593Smuzhiyun #define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02) 16*4882a593Smuzhiyun #define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04) 17*4882a593Smuzhiyun #define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06) 18*4882a593Smuzhiyun #define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_BASE (0xfffee300) 21*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0) 22*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2) 23*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4) 24*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8) 25*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca) 26*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc) 27*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce) 28*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0) 29*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2) 30*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4) 31*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6) 32*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8) 33*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda) 34*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0) 35*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4) 36*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea) 37*4882a593Smuzhiyun #define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* LCD DMA block numbers */ 40*4882a593Smuzhiyun enum { 41*4882a593Smuzhiyun OMAP_LCD_DMA_B1_TOP, 42*4882a593Smuzhiyun OMAP_LCD_DMA_B1_BOTTOM, 43*4882a593Smuzhiyun OMAP_LCD_DMA_B2_TOP, 44*4882a593Smuzhiyun OMAP_LCD_DMA_B2_BOTTOM 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* LCD DMA functions */ 48*4882a593Smuzhiyun extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), 49*4882a593Smuzhiyun void *data); 50*4882a593Smuzhiyun extern void omap_free_lcd_dma(void); 51*4882a593Smuzhiyun extern void omap_setup_lcd_dma(void); 52*4882a593Smuzhiyun extern void omap_enable_lcd_dma(void); 53*4882a593Smuzhiyun extern void omap_stop_lcd_dma(void); 54*4882a593Smuzhiyun extern void omap_set_lcd_dma_ext_controller(int external); 55*4882a593Smuzhiyun extern void omap_set_lcd_dma_single_transfer(int single); 56*4882a593Smuzhiyun extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, 57*4882a593Smuzhiyun int data_type); 58*4882a593Smuzhiyun extern void omap_set_lcd_dma_b1_rotation(int rotate); 59*4882a593Smuzhiyun extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres); 60*4882a593Smuzhiyun extern void omap_set_lcd_dma_b1_mirror(int mirror); 61*4882a593Smuzhiyun extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun extern int omap_lcd_dma_running(void); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* __MACH_OMAP1_LCD_DMA_H__ */ 66