1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/plat-omap/include/mach/irqs.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) Greg Lonnon 2001 6*4882a593Smuzhiyun * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2009 Texas Instruments 9*4882a593Smuzhiyun * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 12*4882a593Smuzhiyun * are different. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __ASM_ARCH_OMAP15XX_IRQS_H 16*4882a593Smuzhiyun #define __ASM_ARCH_OMAP15XX_IRQS_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * IRQ numbers for interrupt handler 1 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define INT_CAMERA (NR_IRQS_LEGACY + 1) 25*4882a593Smuzhiyun #define INT_FIQ (NR_IRQS_LEGACY + 3) 26*4882a593Smuzhiyun #define INT_RTDX (NR_IRQS_LEGACY + 6) 27*4882a593Smuzhiyun #define INT_DSP_MMU_ABORT (NR_IRQS_LEGACY + 7) 28*4882a593Smuzhiyun #define INT_HOST (NR_IRQS_LEGACY + 8) 29*4882a593Smuzhiyun #define INT_ABORT (NR_IRQS_LEGACY + 9) 30*4882a593Smuzhiyun #define INT_BRIDGE_PRIV (NR_IRQS_LEGACY + 13) 31*4882a593Smuzhiyun #define INT_GPIO_BANK1 (NR_IRQS_LEGACY + 14) 32*4882a593Smuzhiyun #define INT_UART3 (NR_IRQS_LEGACY + 15) 33*4882a593Smuzhiyun #define INT_TIMER3 (NR_IRQS_LEGACY + 16) 34*4882a593Smuzhiyun #define INT_DMA_CH0_6 (NR_IRQS_LEGACY + 19) 35*4882a593Smuzhiyun #define INT_DMA_CH1_7 (NR_IRQS_LEGACY + 20) 36*4882a593Smuzhiyun #define INT_DMA_CH2_8 (NR_IRQS_LEGACY + 21) 37*4882a593Smuzhiyun #define INT_DMA_CH3 (NR_IRQS_LEGACY + 22) 38*4882a593Smuzhiyun #define INT_DMA_CH4 (NR_IRQS_LEGACY + 23) 39*4882a593Smuzhiyun #define INT_DMA_CH5 (NR_IRQS_LEGACY + 24) 40*4882a593Smuzhiyun #define INT_TIMER1 (NR_IRQS_LEGACY + 26) 41*4882a593Smuzhiyun #define INT_WD_TIMER (NR_IRQS_LEGACY + 27) 42*4882a593Smuzhiyun #define INT_BRIDGE_PUB (NR_IRQS_LEGACY + 28) 43*4882a593Smuzhiyun #define INT_TIMER2 (NR_IRQS_LEGACY + 30) 44*4882a593Smuzhiyun #define INT_LCD_CTRL (NR_IRQS_LEGACY + 31) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * OMAP-1510 specific IRQ numbers for interrupt handler 1 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define INT_1510_IH2_IRQ (NR_IRQS_LEGACY + 0) 50*4882a593Smuzhiyun #define INT_1510_RES2 (NR_IRQS_LEGACY + 2) 51*4882a593Smuzhiyun #define INT_1510_SPI_TX (NR_IRQS_LEGACY + 4) 52*4882a593Smuzhiyun #define INT_1510_SPI_RX (NR_IRQS_LEGACY + 5) 53*4882a593Smuzhiyun #define INT_1510_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) 54*4882a593Smuzhiyun #define INT_1510_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) 55*4882a593Smuzhiyun #define INT_1510_RES12 (NR_IRQS_LEGACY + 12) 56*4882a593Smuzhiyun #define INT_1510_LB_MMU (NR_IRQS_LEGACY + 17) 57*4882a593Smuzhiyun #define INT_1510_RES18 (NR_IRQS_LEGACY + 18) 58*4882a593Smuzhiyun #define INT_1510_LOCAL_BUS (NR_IRQS_LEGACY + 29) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * OMAP-1610 specific IRQ numbers for interrupt handler 1 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun #define INT_1610_IH2_IRQ INT_1510_IH2_IRQ 64*4882a593Smuzhiyun #define INT_1610_IH2_FIQ (NR_IRQS_LEGACY + 2) 65*4882a593Smuzhiyun #define INT_1610_McBSP2_TX (NR_IRQS_LEGACY + 4) 66*4882a593Smuzhiyun #define INT_1610_McBSP2_RX (NR_IRQS_LEGACY + 5) 67*4882a593Smuzhiyun #define INT_1610_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) 68*4882a593Smuzhiyun #define INT_1610_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) 69*4882a593Smuzhiyun #define INT_1610_LCD_LINE (NR_IRQS_LEGACY + 12) 70*4882a593Smuzhiyun #define INT_1610_GPTIMER1 (NR_IRQS_LEGACY + 17) 71*4882a593Smuzhiyun #define INT_1610_GPTIMER2 (NR_IRQS_LEGACY + 18) 72*4882a593Smuzhiyun #define INT_1610_SSR_FIFO_0 (NR_IRQS_LEGACY + 29) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * OMAP-7xx specific IRQ numbers for interrupt handler 1 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun #define INT_7XX_IH2_FIQ (NR_IRQS_LEGACY + 0) 78*4882a593Smuzhiyun #define INT_7XX_IH2_IRQ (NR_IRQS_LEGACY + 1) 79*4882a593Smuzhiyun #define INT_7XX_USB_NON_ISO (NR_IRQS_LEGACY + 2) 80*4882a593Smuzhiyun #define INT_7XX_USB_ISO (NR_IRQS_LEGACY + 3) 81*4882a593Smuzhiyun #define INT_7XX_ICR (NR_IRQS_LEGACY + 4) 82*4882a593Smuzhiyun #define INT_7XX_EAC (NR_IRQS_LEGACY + 5) 83*4882a593Smuzhiyun #define INT_7XX_GPIO_BANK1 (NR_IRQS_LEGACY + 6) 84*4882a593Smuzhiyun #define INT_7XX_GPIO_BANK2 (NR_IRQS_LEGACY + 7) 85*4882a593Smuzhiyun #define INT_7XX_GPIO_BANK3 (NR_IRQS_LEGACY + 8) 86*4882a593Smuzhiyun #define INT_7XX_McBSP2TX (NR_IRQS_LEGACY + 10) 87*4882a593Smuzhiyun #define INT_7XX_McBSP2RX (NR_IRQS_LEGACY + 11) 88*4882a593Smuzhiyun #define INT_7XX_McBSP2RX_OVF (NR_IRQS_LEGACY + 12) 89*4882a593Smuzhiyun #define INT_7XX_LCD_LINE (NR_IRQS_LEGACY + 14) 90*4882a593Smuzhiyun #define INT_7XX_GSM_PROTECT (NR_IRQS_LEGACY + 15) 91*4882a593Smuzhiyun #define INT_7XX_TIMER3 (NR_IRQS_LEGACY + 16) 92*4882a593Smuzhiyun #define INT_7XX_GPIO_BANK5 (NR_IRQS_LEGACY + 17) 93*4882a593Smuzhiyun #define INT_7XX_GPIO_BANK6 (NR_IRQS_LEGACY + 18) 94*4882a593Smuzhiyun #define INT_7XX_SPGIO_WR (NR_IRQS_LEGACY + 29) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * IRQ numbers for interrupt handler 2 98*4882a593Smuzhiyun * 99*4882a593Smuzhiyun * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below 100*4882a593Smuzhiyun */ 101*4882a593Smuzhiyun #define IH2_BASE (NR_IRQS_LEGACY + 32) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define INT_KEYBOARD (1 + IH2_BASE) 104*4882a593Smuzhiyun #define INT_uWireTX (2 + IH2_BASE) 105*4882a593Smuzhiyun #define INT_uWireRX (3 + IH2_BASE) 106*4882a593Smuzhiyun #define INT_I2C (4 + IH2_BASE) 107*4882a593Smuzhiyun #define INT_MPUIO (5 + IH2_BASE) 108*4882a593Smuzhiyun #define INT_USB_HHC_1 (6 + IH2_BASE) 109*4882a593Smuzhiyun #define INT_McBSP3TX (10 + IH2_BASE) 110*4882a593Smuzhiyun #define INT_McBSP3RX (11 + IH2_BASE) 111*4882a593Smuzhiyun #define INT_McBSP1TX (12 + IH2_BASE) 112*4882a593Smuzhiyun #define INT_McBSP1RX (13 + IH2_BASE) 113*4882a593Smuzhiyun #define INT_UART1 (14 + IH2_BASE) 114*4882a593Smuzhiyun #define INT_UART2 (15 + IH2_BASE) 115*4882a593Smuzhiyun #define INT_BT_MCSI1TX (16 + IH2_BASE) 116*4882a593Smuzhiyun #define INT_BT_MCSI1RX (17 + IH2_BASE) 117*4882a593Smuzhiyun #define INT_SOSSI_MATCH (19 + IH2_BASE) 118*4882a593Smuzhiyun #define INT_USB_W2FC (20 + IH2_BASE) 119*4882a593Smuzhiyun #define INT_1WIRE (21 + IH2_BASE) 120*4882a593Smuzhiyun #define INT_OS_TIMER (22 + IH2_BASE) 121*4882a593Smuzhiyun #define INT_MMC (23 + IH2_BASE) 122*4882a593Smuzhiyun #define INT_GAUGE_32K (24 + IH2_BASE) 123*4882a593Smuzhiyun #define INT_RTC_TIMER (25 + IH2_BASE) 124*4882a593Smuzhiyun #define INT_RTC_ALARM (26 + IH2_BASE) 125*4882a593Smuzhiyun #define INT_MEM_STICK (27 + IH2_BASE) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* 128*4882a593Smuzhiyun * OMAP-1510 specific IRQ numbers for interrupt handler 2 129*4882a593Smuzhiyun */ 130*4882a593Smuzhiyun #define INT_1510_DSP_MMU (28 + IH2_BASE) 131*4882a593Smuzhiyun #define INT_1510_COM_SPI_RO (31 + IH2_BASE) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* 134*4882a593Smuzhiyun * OMAP-1610 specific IRQ numbers for interrupt handler 2 135*4882a593Smuzhiyun */ 136*4882a593Smuzhiyun #define INT_1610_FAC (0 + IH2_BASE) 137*4882a593Smuzhiyun #define INT_1610_USB_HHC_2 (7 + IH2_BASE) 138*4882a593Smuzhiyun #define INT_1610_USB_OTG (8 + IH2_BASE) 139*4882a593Smuzhiyun #define INT_1610_SoSSI (9 + IH2_BASE) 140*4882a593Smuzhiyun #define INT_1610_SoSSI_MATCH (19 + IH2_BASE) 141*4882a593Smuzhiyun #define INT_1610_DSP_MMU (28 + IH2_BASE) 142*4882a593Smuzhiyun #define INT_1610_McBSP2RX_OF (31 + IH2_BASE) 143*4882a593Smuzhiyun #define INT_1610_STI (32 + IH2_BASE) 144*4882a593Smuzhiyun #define INT_1610_STI_WAKEUP (33 + IH2_BASE) 145*4882a593Smuzhiyun #define INT_1610_GPTIMER3 (34 + IH2_BASE) 146*4882a593Smuzhiyun #define INT_1610_GPTIMER4 (35 + IH2_BASE) 147*4882a593Smuzhiyun #define INT_1610_GPTIMER5 (36 + IH2_BASE) 148*4882a593Smuzhiyun #define INT_1610_GPTIMER6 (37 + IH2_BASE) 149*4882a593Smuzhiyun #define INT_1610_GPTIMER7 (38 + IH2_BASE) 150*4882a593Smuzhiyun #define INT_1610_GPTIMER8 (39 + IH2_BASE) 151*4882a593Smuzhiyun #define INT_1610_GPIO_BANK2 (40 + IH2_BASE) 152*4882a593Smuzhiyun #define INT_1610_GPIO_BANK3 (41 + IH2_BASE) 153*4882a593Smuzhiyun #define INT_1610_MMC2 (42 + IH2_BASE) 154*4882a593Smuzhiyun #define INT_1610_CF (43 + IH2_BASE) 155*4882a593Smuzhiyun #define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) 156*4882a593Smuzhiyun #define INT_1610_GPIO_BANK4 (48 + IH2_BASE) 157*4882a593Smuzhiyun #define INT_1610_SPI (49 + IH2_BASE) 158*4882a593Smuzhiyun #define INT_1610_DMA_CH6 (53 + IH2_BASE) 159*4882a593Smuzhiyun #define INT_1610_DMA_CH7 (54 + IH2_BASE) 160*4882a593Smuzhiyun #define INT_1610_DMA_CH8 (55 + IH2_BASE) 161*4882a593Smuzhiyun #define INT_1610_DMA_CH9 (56 + IH2_BASE) 162*4882a593Smuzhiyun #define INT_1610_DMA_CH10 (57 + IH2_BASE) 163*4882a593Smuzhiyun #define INT_1610_DMA_CH11 (58 + IH2_BASE) 164*4882a593Smuzhiyun #define INT_1610_DMA_CH12 (59 + IH2_BASE) 165*4882a593Smuzhiyun #define INT_1610_DMA_CH13 (60 + IH2_BASE) 166*4882a593Smuzhiyun #define INT_1610_DMA_CH14 (61 + IH2_BASE) 167*4882a593Smuzhiyun #define INT_1610_DMA_CH15 (62 + IH2_BASE) 168*4882a593Smuzhiyun #define INT_1610_NAND (63 + IH2_BASE) 169*4882a593Smuzhiyun #define INT_1610_SHA1MD5 (91 + IH2_BASE) 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* 172*4882a593Smuzhiyun * OMAP-7xx specific IRQ numbers for interrupt handler 2 173*4882a593Smuzhiyun */ 174*4882a593Smuzhiyun #define INT_7XX_HW_ERRORS (0 + IH2_BASE) 175*4882a593Smuzhiyun #define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) 176*4882a593Smuzhiyun #define INT_7XX_CFCD (2 + IH2_BASE) 177*4882a593Smuzhiyun #define INT_7XX_CFIREQ (3 + IH2_BASE) 178*4882a593Smuzhiyun #define INT_7XX_I2C (4 + IH2_BASE) 179*4882a593Smuzhiyun #define INT_7XX_PCC (5 + IH2_BASE) 180*4882a593Smuzhiyun #define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) 181*4882a593Smuzhiyun #define INT_7XX_SPI_100K_1 (7 + IH2_BASE) 182*4882a593Smuzhiyun #define INT_7XX_SYREN_SPI (8 + IH2_BASE) 183*4882a593Smuzhiyun #define INT_7XX_VLYNQ (9 + IH2_BASE) 184*4882a593Smuzhiyun #define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) 185*4882a593Smuzhiyun #define INT_7XX_McBSP1TX (11 + IH2_BASE) 186*4882a593Smuzhiyun #define INT_7XX_McBSP1RX (12 + IH2_BASE) 187*4882a593Smuzhiyun #define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) 188*4882a593Smuzhiyun #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) 189*4882a593Smuzhiyun #define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) 190*4882a593Smuzhiyun #define INT_7XX_MCSI (16 + IH2_BASE) 191*4882a593Smuzhiyun #define INT_7XX_uWireTX (17 + IH2_BASE) 192*4882a593Smuzhiyun #define INT_7XX_uWireRX (18 + IH2_BASE) 193*4882a593Smuzhiyun #define INT_7XX_SMC_CD (19 + IH2_BASE) 194*4882a593Smuzhiyun #define INT_7XX_SMC_IREQ (20 + IH2_BASE) 195*4882a593Smuzhiyun #define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) 196*4882a593Smuzhiyun #define INT_7XX_TIMER32K (22 + IH2_BASE) 197*4882a593Smuzhiyun #define INT_7XX_MMC_SDIO (23 + IH2_BASE) 198*4882a593Smuzhiyun #define INT_7XX_UPLD (24 + IH2_BASE) 199*4882a593Smuzhiyun #define INT_7XX_USB_HHC_1 (27 + IH2_BASE) 200*4882a593Smuzhiyun #define INT_7XX_USB_HHC_2 (28 + IH2_BASE) 201*4882a593Smuzhiyun #define INT_7XX_USB_GENI (29 + IH2_BASE) 202*4882a593Smuzhiyun #define INT_7XX_USB_OTG (30 + IH2_BASE) 203*4882a593Smuzhiyun #define INT_7XX_CAMERA_IF (31 + IH2_BASE) 204*4882a593Smuzhiyun #define INT_7XX_RNG (32 + IH2_BASE) 205*4882a593Smuzhiyun #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) 206*4882a593Smuzhiyun #define INT_7XX_DBB_RF_EN (34 + IH2_BASE) 207*4882a593Smuzhiyun #define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) 208*4882a593Smuzhiyun #define INT_7XX_SHA1_MD5 (36 + IH2_BASE) 209*4882a593Smuzhiyun #define INT_7XX_SPI_100K_2 (37 + IH2_BASE) 210*4882a593Smuzhiyun #define INT_7XX_RNG_IDLE (38 + IH2_BASE) 211*4882a593Smuzhiyun #define INT_7XX_MPUIO (39 + IH2_BASE) 212*4882a593Smuzhiyun #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) 213*4882a593Smuzhiyun #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) 214*4882a593Smuzhiyun #define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) 215*4882a593Smuzhiyun #define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) 216*4882a593Smuzhiyun #define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) 217*4882a593Smuzhiyun #define INT_7XX_DMA_CH6 (53 + IH2_BASE) 218*4882a593Smuzhiyun #define INT_7XX_DMA_CH7 (54 + IH2_BASE) 219*4882a593Smuzhiyun #define INT_7XX_DMA_CH8 (55 + IH2_BASE) 220*4882a593Smuzhiyun #define INT_7XX_DMA_CH9 (56 + IH2_BASE) 221*4882a593Smuzhiyun #define INT_7XX_DMA_CH10 (57 + IH2_BASE) 222*4882a593Smuzhiyun #define INT_7XX_DMA_CH11 (58 + IH2_BASE) 223*4882a593Smuzhiyun #define INT_7XX_DMA_CH12 (59 + IH2_BASE) 224*4882a593Smuzhiyun #define INT_7XX_DMA_CH13 (60 + IH2_BASE) 225*4882a593Smuzhiyun #define INT_7XX_DMA_CH14 (61 + IH2_BASE) 226*4882a593Smuzhiyun #define INT_7XX_DMA_CH15 (62 + IH2_BASE) 227*4882a593Smuzhiyun #define INT_7XX_NAND (63 + IH2_BASE) 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and 230*4882a593Smuzhiyun * 16 MPUIO lines */ 231*4882a593Smuzhiyun #define OMAP_MAX_GPIO_LINES 192 232*4882a593Smuzhiyun #define IH_GPIO_BASE (128 + IH2_BASE) 233*4882a593Smuzhiyun #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) 234*4882a593Smuzhiyun #define OMAP_IRQ_END (IH_MPUIO_BASE + 16) 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /* External FPGA handles interrupts on Innovator boards */ 237*4882a593Smuzhiyun #define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) 238*4882a593Smuzhiyun #ifdef CONFIG_MACH_OMAP_INNOVATOR 239*4882a593Smuzhiyun #define OMAP_FPGA_NR_IRQS 24 240*4882a593Smuzhiyun #else 241*4882a593Smuzhiyun #define OMAP_FPGA_NR_IRQS 0 242*4882a593Smuzhiyun #endif 243*4882a593Smuzhiyun #define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #define OMAP_IRQ_BIT(irq) (1 << ((irq - NR_IRQS_LEGACY) % 32)) 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun #ifdef CONFIG_FIQ 248*4882a593Smuzhiyun #define FIQ_START 1024 249*4882a593Smuzhiyun #endif 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #endif 252