1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * OMAP7xx specific gpio init
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author:
7*4882a593Smuzhiyun * Charulatha V <charu@ti.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
11*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
15*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16*4882a593Smuzhiyun * GNU General Public License for more details.
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/gpio.h>
20*4882a593Smuzhiyun #include <linux/platform_data/gpio-omap.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <mach/irqs.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "soc.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define OMAP7XX_GPIO1_BASE 0xfffbc000
27*4882a593Smuzhiyun #define OMAP7XX_GPIO2_BASE 0xfffbc800
28*4882a593Smuzhiyun #define OMAP7XX_GPIO3_BASE 0xfffbd000
29*4882a593Smuzhiyun #define OMAP7XX_GPIO4_BASE 0xfffbd800
30*4882a593Smuzhiyun #define OMAP7XX_GPIO5_BASE 0xfffbe000
31*4882a593Smuzhiyun #define OMAP7XX_GPIO6_BASE 0xfffbe800
32*4882a593Smuzhiyun #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* mpu gpio */
35*4882a593Smuzhiyun static struct resource omap7xx_mpu_gpio_resources[] = {
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun .start = OMAP1_MPUIO_VBASE,
38*4882a593Smuzhiyun .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
39*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
40*4882a593Smuzhiyun },
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun .start = INT_7XX_MPUIO,
43*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
44*4882a593Smuzhiyun },
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
48*4882a593Smuzhiyun .revision = USHRT_MAX,
49*4882a593Smuzhiyun .direction = OMAP_MPUIO_IO_CNTL / 2,
50*4882a593Smuzhiyun .datain = OMAP_MPUIO_INPUT_LATCH / 2,
51*4882a593Smuzhiyun .dataout = OMAP_MPUIO_OUTPUT / 2,
52*4882a593Smuzhiyun .irqstatus = OMAP_MPUIO_GPIO_INT / 2,
53*4882a593Smuzhiyun .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2,
54*4882a593Smuzhiyun .irqenable_inv = true,
55*4882a593Smuzhiyun .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static struct omap_gpio_platform_data omap7xx_mpu_gpio_config = {
59*4882a593Smuzhiyun .is_mpuio = true,
60*4882a593Smuzhiyun .bank_width = 16,
61*4882a593Smuzhiyun .bank_stride = 2,
62*4882a593Smuzhiyun .regs = &omap7xx_mpuio_regs,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static struct platform_device omap7xx_mpu_gpio = {
66*4882a593Smuzhiyun .name = "omap_gpio",
67*4882a593Smuzhiyun .id = 0,
68*4882a593Smuzhiyun .dev = {
69*4882a593Smuzhiyun .platform_data = &omap7xx_mpu_gpio_config,
70*4882a593Smuzhiyun },
71*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(omap7xx_mpu_gpio_resources),
72*4882a593Smuzhiyun .resource = omap7xx_mpu_gpio_resources,
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* gpio1 */
76*4882a593Smuzhiyun static struct resource omap7xx_gpio1_resources[] = {
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun .start = OMAP7XX_GPIO1_BASE,
79*4882a593Smuzhiyun .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1,
80*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
81*4882a593Smuzhiyun },
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun .start = INT_7XX_GPIO_BANK1,
84*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
85*4882a593Smuzhiyun },
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
89*4882a593Smuzhiyun .revision = USHRT_MAX,
90*4882a593Smuzhiyun .direction = OMAP7XX_GPIO_DIR_CONTROL,
91*4882a593Smuzhiyun .datain = OMAP7XX_GPIO_DATA_INPUT,
92*4882a593Smuzhiyun .dataout = OMAP7XX_GPIO_DATA_OUTPUT,
93*4882a593Smuzhiyun .irqstatus = OMAP7XX_GPIO_INT_STATUS,
94*4882a593Smuzhiyun .irqenable = OMAP7XX_GPIO_INT_MASK,
95*4882a593Smuzhiyun .irqenable_inv = true,
96*4882a593Smuzhiyun .irqctrl = OMAP7XX_GPIO_INT_CONTROL,
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static struct omap_gpio_platform_data omap7xx_gpio1_config = {
100*4882a593Smuzhiyun .bank_width = 32,
101*4882a593Smuzhiyun .regs = &omap7xx_gpio_regs,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static struct platform_device omap7xx_gpio1 = {
105*4882a593Smuzhiyun .name = "omap_gpio",
106*4882a593Smuzhiyun .id = 1,
107*4882a593Smuzhiyun .dev = {
108*4882a593Smuzhiyun .platform_data = &omap7xx_gpio1_config,
109*4882a593Smuzhiyun },
110*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(omap7xx_gpio1_resources),
111*4882a593Smuzhiyun .resource = omap7xx_gpio1_resources,
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* gpio2 */
115*4882a593Smuzhiyun static struct resource omap7xx_gpio2_resources[] = {
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun .start = OMAP7XX_GPIO2_BASE,
118*4882a593Smuzhiyun .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1,
119*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
120*4882a593Smuzhiyun },
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun .start = INT_7XX_GPIO_BANK2,
123*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
124*4882a593Smuzhiyun },
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun static struct omap_gpio_platform_data omap7xx_gpio2_config = {
128*4882a593Smuzhiyun .bank_width = 32,
129*4882a593Smuzhiyun .regs = &omap7xx_gpio_regs,
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun static struct platform_device omap7xx_gpio2 = {
133*4882a593Smuzhiyun .name = "omap_gpio",
134*4882a593Smuzhiyun .id = 2,
135*4882a593Smuzhiyun .dev = {
136*4882a593Smuzhiyun .platform_data = &omap7xx_gpio2_config,
137*4882a593Smuzhiyun },
138*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(omap7xx_gpio2_resources),
139*4882a593Smuzhiyun .resource = omap7xx_gpio2_resources,
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* gpio3 */
143*4882a593Smuzhiyun static struct resource omap7xx_gpio3_resources[] = {
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun .start = OMAP7XX_GPIO3_BASE,
146*4882a593Smuzhiyun .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1,
147*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
148*4882a593Smuzhiyun },
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun .start = INT_7XX_GPIO_BANK3,
151*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
152*4882a593Smuzhiyun },
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun static struct omap_gpio_platform_data omap7xx_gpio3_config = {
156*4882a593Smuzhiyun .bank_width = 32,
157*4882a593Smuzhiyun .regs = &omap7xx_gpio_regs,
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun static struct platform_device omap7xx_gpio3 = {
161*4882a593Smuzhiyun .name = "omap_gpio",
162*4882a593Smuzhiyun .id = 3,
163*4882a593Smuzhiyun .dev = {
164*4882a593Smuzhiyun .platform_data = &omap7xx_gpio3_config,
165*4882a593Smuzhiyun },
166*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(omap7xx_gpio3_resources),
167*4882a593Smuzhiyun .resource = omap7xx_gpio3_resources,
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /* gpio4 */
171*4882a593Smuzhiyun static struct resource omap7xx_gpio4_resources[] = {
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun .start = OMAP7XX_GPIO4_BASE,
174*4882a593Smuzhiyun .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1,
175*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
176*4882a593Smuzhiyun },
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun .start = INT_7XX_GPIO_BANK4,
179*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
180*4882a593Smuzhiyun },
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static struct omap_gpio_platform_data omap7xx_gpio4_config = {
184*4882a593Smuzhiyun .bank_width = 32,
185*4882a593Smuzhiyun .regs = &omap7xx_gpio_regs,
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun static struct platform_device omap7xx_gpio4 = {
189*4882a593Smuzhiyun .name = "omap_gpio",
190*4882a593Smuzhiyun .id = 4,
191*4882a593Smuzhiyun .dev = {
192*4882a593Smuzhiyun .platform_data = &omap7xx_gpio4_config,
193*4882a593Smuzhiyun },
194*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(omap7xx_gpio4_resources),
195*4882a593Smuzhiyun .resource = omap7xx_gpio4_resources,
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* gpio5 */
199*4882a593Smuzhiyun static struct resource omap7xx_gpio5_resources[] = {
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun .start = OMAP7XX_GPIO5_BASE,
202*4882a593Smuzhiyun .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1,
203*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
204*4882a593Smuzhiyun },
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun .start = INT_7XX_GPIO_BANK5,
207*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
208*4882a593Smuzhiyun },
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun static struct omap_gpio_platform_data omap7xx_gpio5_config = {
212*4882a593Smuzhiyun .bank_width = 32,
213*4882a593Smuzhiyun .regs = &omap7xx_gpio_regs,
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun static struct platform_device omap7xx_gpio5 = {
217*4882a593Smuzhiyun .name = "omap_gpio",
218*4882a593Smuzhiyun .id = 5,
219*4882a593Smuzhiyun .dev = {
220*4882a593Smuzhiyun .platform_data = &omap7xx_gpio5_config,
221*4882a593Smuzhiyun },
222*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(omap7xx_gpio5_resources),
223*4882a593Smuzhiyun .resource = omap7xx_gpio5_resources,
224*4882a593Smuzhiyun };
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* gpio6 */
227*4882a593Smuzhiyun static struct resource omap7xx_gpio6_resources[] = {
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun .start = OMAP7XX_GPIO6_BASE,
230*4882a593Smuzhiyun .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1,
231*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
232*4882a593Smuzhiyun },
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun .start = INT_7XX_GPIO_BANK6,
235*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
236*4882a593Smuzhiyun },
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun static struct omap_gpio_platform_data omap7xx_gpio6_config = {
240*4882a593Smuzhiyun .bank_width = 32,
241*4882a593Smuzhiyun .regs = &omap7xx_gpio_regs,
242*4882a593Smuzhiyun };
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun static struct platform_device omap7xx_gpio6 = {
245*4882a593Smuzhiyun .name = "omap_gpio",
246*4882a593Smuzhiyun .id = 6,
247*4882a593Smuzhiyun .dev = {
248*4882a593Smuzhiyun .platform_data = &omap7xx_gpio6_config,
249*4882a593Smuzhiyun },
250*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(omap7xx_gpio6_resources),
251*4882a593Smuzhiyun .resource = omap7xx_gpio6_resources,
252*4882a593Smuzhiyun };
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun static struct platform_device *omap7xx_gpio_dev[] __initdata = {
255*4882a593Smuzhiyun &omap7xx_mpu_gpio,
256*4882a593Smuzhiyun &omap7xx_gpio1,
257*4882a593Smuzhiyun &omap7xx_gpio2,
258*4882a593Smuzhiyun &omap7xx_gpio3,
259*4882a593Smuzhiyun &omap7xx_gpio4,
260*4882a593Smuzhiyun &omap7xx_gpio5,
261*4882a593Smuzhiyun &omap7xx_gpio6,
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /*
265*4882a593Smuzhiyun * omap7xx_gpio_init needs to be done before
266*4882a593Smuzhiyun * machine_init functions access gpio APIs.
267*4882a593Smuzhiyun * Hence omap7xx_gpio_init is a postcore_initcall.
268*4882a593Smuzhiyun */
omap7xx_gpio_init(void)269*4882a593Smuzhiyun static int __init omap7xx_gpio_init(void)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun int i;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun if (!cpu_is_omap7xx())
274*4882a593Smuzhiyun return -EINVAL;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
277*4882a593Smuzhiyun platform_device_register(omap7xx_gpio_dev[i]);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return 0;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun postcore_initcall(omap7xx_gpio_init);
282