1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * OMAP15xx specific gpio init
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author:
7*4882a593Smuzhiyun * Charulatha V <charu@ti.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
11*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
15*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16*4882a593Smuzhiyun * GNU General Public License for more details.
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/gpio.h>
20*4882a593Smuzhiyun #include <linux/platform_data/gpio-omap.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <mach/irqs.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
25*4882a593Smuzhiyun #define OMAP1510_GPIO_BASE 0xFFFCE000
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* gpio1 */
28*4882a593Smuzhiyun static struct resource omap15xx_mpu_gpio_resources[] = {
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun .start = OMAP1_MPUIO_VBASE,
31*4882a593Smuzhiyun .end = OMAP1_MPUIO_VBASE + SZ_2K - 1,
32*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
33*4882a593Smuzhiyun },
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun .start = INT_MPUIO,
36*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
37*4882a593Smuzhiyun },
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
41*4882a593Smuzhiyun .revision = USHRT_MAX,
42*4882a593Smuzhiyun .direction = OMAP_MPUIO_IO_CNTL,
43*4882a593Smuzhiyun .datain = OMAP_MPUIO_INPUT_LATCH,
44*4882a593Smuzhiyun .dataout = OMAP_MPUIO_OUTPUT,
45*4882a593Smuzhiyun .irqstatus = OMAP_MPUIO_GPIO_INT,
46*4882a593Smuzhiyun .irqenable = OMAP_MPUIO_GPIO_MASKIT,
47*4882a593Smuzhiyun .irqenable_inv = true,
48*4882a593Smuzhiyun .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE,
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static struct omap_gpio_platform_data omap15xx_mpu_gpio_config = {
52*4882a593Smuzhiyun .is_mpuio = true,
53*4882a593Smuzhiyun .bank_width = 16,
54*4882a593Smuzhiyun .bank_stride = 1,
55*4882a593Smuzhiyun .regs = &omap15xx_mpuio_regs,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static struct platform_device omap15xx_mpu_gpio = {
59*4882a593Smuzhiyun .name = "omap_gpio",
60*4882a593Smuzhiyun .id = 0,
61*4882a593Smuzhiyun .dev = {
62*4882a593Smuzhiyun .platform_data = &omap15xx_mpu_gpio_config,
63*4882a593Smuzhiyun },
64*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(omap15xx_mpu_gpio_resources),
65*4882a593Smuzhiyun .resource = omap15xx_mpu_gpio_resources,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* gpio2 */
69*4882a593Smuzhiyun static struct resource omap15xx_gpio_resources[] = {
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun .start = OMAP1510_GPIO_BASE,
72*4882a593Smuzhiyun .end = OMAP1510_GPIO_BASE + SZ_2K - 1,
73*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
74*4882a593Smuzhiyun },
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun .start = INT_GPIO_BANK1,
77*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
78*4882a593Smuzhiyun },
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
82*4882a593Smuzhiyun .revision = USHRT_MAX,
83*4882a593Smuzhiyun .direction = OMAP1510_GPIO_DIR_CONTROL,
84*4882a593Smuzhiyun .datain = OMAP1510_GPIO_DATA_INPUT,
85*4882a593Smuzhiyun .dataout = OMAP1510_GPIO_DATA_OUTPUT,
86*4882a593Smuzhiyun .irqstatus = OMAP1510_GPIO_INT_STATUS,
87*4882a593Smuzhiyun .irqenable = OMAP1510_GPIO_INT_MASK,
88*4882a593Smuzhiyun .irqenable_inv = true,
89*4882a593Smuzhiyun .irqctrl = OMAP1510_GPIO_INT_CONTROL,
90*4882a593Smuzhiyun .pinctrl = OMAP1510_GPIO_PIN_CONTROL,
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static struct omap_gpio_platform_data omap15xx_gpio_config = {
94*4882a593Smuzhiyun .bank_width = 16,
95*4882a593Smuzhiyun .regs = &omap15xx_gpio_regs,
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static struct platform_device omap15xx_gpio = {
99*4882a593Smuzhiyun .name = "omap_gpio",
100*4882a593Smuzhiyun .id = 1,
101*4882a593Smuzhiyun .dev = {
102*4882a593Smuzhiyun .platform_data = &omap15xx_gpio_config,
103*4882a593Smuzhiyun },
104*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(omap15xx_gpio_resources),
105*4882a593Smuzhiyun .resource = omap15xx_gpio_resources,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun * omap15xx_gpio_init needs to be done before
110*4882a593Smuzhiyun * machine_init functions access gpio APIs.
111*4882a593Smuzhiyun * Hence omap15xx_gpio_init is a postcore_initcall.
112*4882a593Smuzhiyun */
omap15xx_gpio_init(void)113*4882a593Smuzhiyun static int __init omap15xx_gpio_init(void)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun if (!cpu_is_omap15xx())
116*4882a593Smuzhiyun return -EINVAL;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun platform_device_register(&omap15xx_mpu_gpio);
119*4882a593Smuzhiyun platform_device_register(&omap15xx_gpio);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return 0;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun postcore_initcall(omap15xx_gpio_init);
124