1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Interrupt handler for OMAP-1510 FPGA 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2001 RidgeRun, Inc. 6*4882a593Smuzhiyun * Author: Greg Lonnon <glonnon@ridgerun.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2002 MontaVista Software, Inc. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 11*4882a593Smuzhiyun * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com> 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASM_ARCH_OMAP_FPGA_H 15*4882a593Smuzhiyun #define __ASM_ARCH_OMAP_FPGA_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * --------------------------------------------------------------------------- 19*4882a593Smuzhiyun * H2/P2 Debug board FPGA 20*4882a593Smuzhiyun * --------------------------------------------------------------------------- 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun /* maps in the FPGA registers and the ETHR registers */ 23*4882a593Smuzhiyun #define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ 24*4882a593Smuzhiyun #define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ 25*4882a593Smuzhiyun #define H2P2_DBG_FPGA_START 0x04000000 /* PA */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) 28*4882a593Smuzhiyun #define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ 29*4882a593Smuzhiyun #define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ 30*4882a593Smuzhiyun #define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ 31*4882a593Smuzhiyun #define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ 32*4882a593Smuzhiyun #define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ 33*4882a593Smuzhiyun #define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ 34*4882a593Smuzhiyun #define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* LEDs definition on debug board (16 LEDs, all physically green) */ 37*4882a593Smuzhiyun #define H2P2_DBG_FPGA_LED_GREEN (1 << 15) 38*4882a593Smuzhiyun #define H2P2_DBG_FPGA_LED_AMBER (1 << 14) 39*4882a593Smuzhiyun #define H2P2_DBG_FPGA_LED_RED (1 << 13) 40*4882a593Smuzhiyun #define H2P2_DBG_FPGA_LED_BLUE (1 << 12) 41*4882a593Smuzhiyun /* cpu0 load-meter LEDs */ 42*4882a593Smuzhiyun #define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... 43*4882a593Smuzhiyun #define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 44*4882a593Smuzhiyun #define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) 47*4882a593Smuzhiyun #define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #endif 50