1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/arch/arm/mach-omap1/board-perseus2.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Modified from board-generic.c
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
8*4882a593Smuzhiyun * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/gpio.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
16*4882a593Smuzhiyun #include <linux/mtd/platnand.h>
17*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
18*4882a593Smuzhiyun #include <linux/input.h>
19*4882a593Smuzhiyun #include <linux/smc91x.h>
20*4882a593Smuzhiyun #include <linux/omapfb.h>
21*4882a593Smuzhiyun #include <linux/platform_data/keypad-omap.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <asm/mach-types.h>
24*4882a593Smuzhiyun #include <asm/mach/arch.h>
25*4882a593Smuzhiyun #include <asm/mach/map.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <mach/tc.h>
28*4882a593Smuzhiyun #include <mach/mux.h>
29*4882a593Smuzhiyun #include "flash.h"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <mach/hardware.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include "iomap.h"
34*4882a593Smuzhiyun #include "common.h"
35*4882a593Smuzhiyun #include "fpga.h"
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static const unsigned int p2_keymap[] = {
38*4882a593Smuzhiyun KEY(0, 0, KEY_UP),
39*4882a593Smuzhiyun KEY(1, 0, KEY_RIGHT),
40*4882a593Smuzhiyun KEY(2, 0, KEY_LEFT),
41*4882a593Smuzhiyun KEY(3, 0, KEY_DOWN),
42*4882a593Smuzhiyun KEY(4, 0, KEY_ENTER),
43*4882a593Smuzhiyun KEY(0, 1, KEY_F10),
44*4882a593Smuzhiyun KEY(1, 1, KEY_SEND),
45*4882a593Smuzhiyun KEY(2, 1, KEY_END),
46*4882a593Smuzhiyun KEY(3, 1, KEY_VOLUMEDOWN),
47*4882a593Smuzhiyun KEY(4, 1, KEY_VOLUMEUP),
48*4882a593Smuzhiyun KEY(5, 1, KEY_RECORD),
49*4882a593Smuzhiyun KEY(0, 2, KEY_F9),
50*4882a593Smuzhiyun KEY(1, 2, KEY_3),
51*4882a593Smuzhiyun KEY(2, 2, KEY_6),
52*4882a593Smuzhiyun KEY(3, 2, KEY_9),
53*4882a593Smuzhiyun KEY(4, 2, KEY_KPDOT),
54*4882a593Smuzhiyun KEY(0, 3, KEY_BACK),
55*4882a593Smuzhiyun KEY(1, 3, KEY_2),
56*4882a593Smuzhiyun KEY(2, 3, KEY_5),
57*4882a593Smuzhiyun KEY(3, 3, KEY_8),
58*4882a593Smuzhiyun KEY(4, 3, KEY_0),
59*4882a593Smuzhiyun KEY(5, 3, KEY_KPSLASH),
60*4882a593Smuzhiyun KEY(0, 4, KEY_HOME),
61*4882a593Smuzhiyun KEY(1, 4, KEY_1),
62*4882a593Smuzhiyun KEY(2, 4, KEY_4),
63*4882a593Smuzhiyun KEY(3, 4, KEY_7),
64*4882a593Smuzhiyun KEY(4, 4, KEY_KPASTERISK),
65*4882a593Smuzhiyun KEY(5, 4, KEY_POWER),
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static struct smc91x_platdata smc91x_info = {
69*4882a593Smuzhiyun .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
70*4882a593Smuzhiyun .leda = RPC_LED_100_10,
71*4882a593Smuzhiyun .ledb = RPC_LED_TX_RX,
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static struct resource smc91x_resources[] = {
75*4882a593Smuzhiyun [0] = {
76*4882a593Smuzhiyun .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
77*4882a593Smuzhiyun .end = H2P2_DBG_FPGA_ETHR_START + 0xf,
78*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
79*4882a593Smuzhiyun },
80*4882a593Smuzhiyun [1] = {
81*4882a593Smuzhiyun .start = INT_7XX_MPU_EXT_NIRQ,
82*4882a593Smuzhiyun .end = 0,
83*4882a593Smuzhiyun .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
84*4882a593Smuzhiyun },
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static struct mtd_partition nor_partitions[] = {
88*4882a593Smuzhiyun /* bootloader (U-Boot, etc) in first sector */
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun .name = "bootloader",
91*4882a593Smuzhiyun .offset = 0,
92*4882a593Smuzhiyun .size = SZ_128K,
93*4882a593Smuzhiyun .mask_flags = MTD_WRITEABLE, /* force read-only */
94*4882a593Smuzhiyun },
95*4882a593Smuzhiyun /* bootloader params in the next sector */
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun .name = "params",
98*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
99*4882a593Smuzhiyun .size = SZ_128K,
100*4882a593Smuzhiyun .mask_flags = 0,
101*4882a593Smuzhiyun },
102*4882a593Smuzhiyun /* kernel */
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun .name = "kernel",
105*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
106*4882a593Smuzhiyun .size = SZ_2M,
107*4882a593Smuzhiyun .mask_flags = 0
108*4882a593Smuzhiyun },
109*4882a593Smuzhiyun /* rest of flash is a file system */
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun .name = "rootfs",
112*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND,
113*4882a593Smuzhiyun .size = MTDPART_SIZ_FULL,
114*4882a593Smuzhiyun .mask_flags = 0
115*4882a593Smuzhiyun },
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static struct physmap_flash_data nor_data = {
119*4882a593Smuzhiyun .width = 2,
120*4882a593Smuzhiyun .set_vpp = omap1_set_vpp,
121*4882a593Smuzhiyun .parts = nor_partitions,
122*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(nor_partitions),
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun static struct resource nor_resource = {
126*4882a593Smuzhiyun .start = OMAP_CS0_PHYS,
127*4882a593Smuzhiyun .end = OMAP_CS0_PHYS + SZ_32M - 1,
128*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static struct platform_device nor_device = {
132*4882a593Smuzhiyun .name = "physmap-flash",
133*4882a593Smuzhiyun .id = 0,
134*4882a593Smuzhiyun .dev = {
135*4882a593Smuzhiyun .platform_data = &nor_data,
136*4882a593Smuzhiyun },
137*4882a593Smuzhiyun .num_resources = 1,
138*4882a593Smuzhiyun .resource = &nor_resource,
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #define P2_NAND_RB_GPIO_PIN 62
142*4882a593Smuzhiyun
nand_dev_ready(struct nand_chip * chip)143*4882a593Smuzhiyun static int nand_dev_ready(struct nand_chip *chip)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun return gpio_get_value(P2_NAND_RB_GPIO_PIN);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun static struct platform_nand_data nand_data = {
149*4882a593Smuzhiyun .chip = {
150*4882a593Smuzhiyun .nr_chips = 1,
151*4882a593Smuzhiyun .chip_offset = 0,
152*4882a593Smuzhiyun .options = NAND_SAMSUNG_LP_OPTIONS,
153*4882a593Smuzhiyun },
154*4882a593Smuzhiyun .ctrl = {
155*4882a593Smuzhiyun .cmd_ctrl = omap1_nand_cmd_ctl,
156*4882a593Smuzhiyun .dev_ready = nand_dev_ready,
157*4882a593Smuzhiyun },
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun static struct resource nand_resource = {
161*4882a593Smuzhiyun .start = OMAP_CS3_PHYS,
162*4882a593Smuzhiyun .end = OMAP_CS3_PHYS + SZ_4K - 1,
163*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun static struct platform_device nand_device = {
167*4882a593Smuzhiyun .name = "gen_nand",
168*4882a593Smuzhiyun .id = 0,
169*4882a593Smuzhiyun .dev = {
170*4882a593Smuzhiyun .platform_data = &nand_data,
171*4882a593Smuzhiyun },
172*4882a593Smuzhiyun .num_resources = 1,
173*4882a593Smuzhiyun .resource = &nand_resource,
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun static struct platform_device smc91x_device = {
177*4882a593Smuzhiyun .name = "smc91x",
178*4882a593Smuzhiyun .id = 0,
179*4882a593Smuzhiyun .dev = {
180*4882a593Smuzhiyun .platform_data = &smc91x_info,
181*4882a593Smuzhiyun },
182*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(smc91x_resources),
183*4882a593Smuzhiyun .resource = smc91x_resources,
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static struct resource kp_resources[] = {
187*4882a593Smuzhiyun [0] = {
188*4882a593Smuzhiyun .start = INT_7XX_MPUIO_KEYPAD,
189*4882a593Smuzhiyun .end = INT_7XX_MPUIO_KEYPAD,
190*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
191*4882a593Smuzhiyun },
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static const struct matrix_keymap_data p2_keymap_data = {
195*4882a593Smuzhiyun .keymap = p2_keymap,
196*4882a593Smuzhiyun .keymap_size = ARRAY_SIZE(p2_keymap),
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun static struct omap_kp_platform_data kp_data = {
200*4882a593Smuzhiyun .rows = 8,
201*4882a593Smuzhiyun .cols = 8,
202*4882a593Smuzhiyun .keymap_data = &p2_keymap_data,
203*4882a593Smuzhiyun .delay = 4,
204*4882a593Smuzhiyun .dbounce = true,
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static struct platform_device kp_device = {
208*4882a593Smuzhiyun .name = "omap-keypad",
209*4882a593Smuzhiyun .id = -1,
210*4882a593Smuzhiyun .dev = {
211*4882a593Smuzhiyun .platform_data = &kp_data,
212*4882a593Smuzhiyun },
213*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(kp_resources),
214*4882a593Smuzhiyun .resource = kp_resources,
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun static struct platform_device *devices[] __initdata = {
218*4882a593Smuzhiyun &nor_device,
219*4882a593Smuzhiyun &nand_device,
220*4882a593Smuzhiyun &smc91x_device,
221*4882a593Smuzhiyun &kp_device,
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun static const struct omap_lcd_config perseus2_lcd_config __initconst = {
225*4882a593Smuzhiyun .ctrl_name = "internal",
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun
perseus2_init_smc91x(void)228*4882a593Smuzhiyun static void __init perseus2_init_smc91x(void)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
231*4882a593Smuzhiyun mdelay(50);
232*4882a593Smuzhiyun __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
233*4882a593Smuzhiyun H2P2_DBG_FPGA_LAN_RESET);
234*4882a593Smuzhiyun mdelay(50);
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
omap_perseus2_init(void)237*4882a593Smuzhiyun static void __init omap_perseus2_init(void)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun /* Early, board-dependent init */
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /*
242*4882a593Smuzhiyun * Hold GSM Reset until needed
243*4882a593Smuzhiyun */
244*4882a593Smuzhiyun omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun /*
247*4882a593Smuzhiyun * UARTs -> done automagically by 8250 driver
248*4882a593Smuzhiyun */
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /*
251*4882a593Smuzhiyun * CSx timings, GPIO Mux ... setup
252*4882a593Smuzhiyun */
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun /* Flash: CS0 timings setup */
255*4882a593Smuzhiyun omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
256*4882a593Smuzhiyun omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /*
259*4882a593Smuzhiyun * Ethernet support through the debug board
260*4882a593Smuzhiyun * CS1 timings setup
261*4882a593Smuzhiyun */
262*4882a593Smuzhiyun omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
263*4882a593Smuzhiyun omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun /*
266*4882a593Smuzhiyun * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
267*4882a593Smuzhiyun * It is used as the Ethernet controller interrupt
268*4882a593Smuzhiyun */
269*4882a593Smuzhiyun omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF,
270*4882a593Smuzhiyun OMAP7XX_IO_CONF_9);
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun perseus2_init_smc91x();
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun BUG_ON(gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0);
275*4882a593Smuzhiyun gpio_direction_input(P2_NAND_RB_GPIO_PIN);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
278*4882a593Smuzhiyun omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun /* Mux pins for keypad */
281*4882a593Smuzhiyun omap_cfg_reg(E2_7XX_KBR0);
282*4882a593Smuzhiyun omap_cfg_reg(J7_7XX_KBR1);
283*4882a593Smuzhiyun omap_cfg_reg(E1_7XX_KBR2);
284*4882a593Smuzhiyun omap_cfg_reg(F3_7XX_KBR3);
285*4882a593Smuzhiyun omap_cfg_reg(D2_7XX_KBR4);
286*4882a593Smuzhiyun omap_cfg_reg(C2_7XX_KBC0);
287*4882a593Smuzhiyun omap_cfg_reg(D3_7XX_KBC1);
288*4882a593Smuzhiyun omap_cfg_reg(E4_7XX_KBC2);
289*4882a593Smuzhiyun omap_cfg_reg(F4_7XX_KBC3);
290*4882a593Smuzhiyun omap_cfg_reg(E3_7XX_KBC4);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun platform_add_devices(devices, ARRAY_SIZE(devices));
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun omap_serial_init();
295*4882a593Smuzhiyun omap_register_i2c_bus(1, 100, NULL, 0);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun omapfb_set_lcd_config(&perseus2_lcd_config);
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun /* Only FPGA needs to be mapped here. All others are done with ioremap */
301*4882a593Smuzhiyun static struct map_desc omap_perseus2_io_desc[] __initdata = {
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun .virtual = H2P2_DBG_FPGA_BASE,
304*4882a593Smuzhiyun .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
305*4882a593Smuzhiyun .length = H2P2_DBG_FPGA_SIZE,
306*4882a593Smuzhiyun .type = MT_DEVICE
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun
omap_perseus2_map_io(void)310*4882a593Smuzhiyun static void __init omap_perseus2_map_io(void)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun omap7xx_map_io();
313*4882a593Smuzhiyun iotable_init(omap_perseus2_io_desc,
314*4882a593Smuzhiyun ARRAY_SIZE(omap_perseus2_io_desc));
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
318*4882a593Smuzhiyun /* Maintainer: Kevin Hilman <kjh@hilman.org> */
319*4882a593Smuzhiyun .atag_offset = 0x100,
320*4882a593Smuzhiyun .map_io = omap_perseus2_map_io,
321*4882a593Smuzhiyun .init_early = omap1_init_early,
322*4882a593Smuzhiyun .init_irq = omap1_init_irq,
323*4882a593Smuzhiyun .handle_irq = omap1_handle_irq,
324*4882a593Smuzhiyun .init_machine = omap_perseus2_init,
325*4882a593Smuzhiyun .init_late = omap1_init_late,
326*4882a593Smuzhiyun .init_time = omap1_timer_init,
327*4882a593Smuzhiyun .restart = omap1_restart,
328*4882a593Smuzhiyun MACHINE_END
329