xref: /OK3568_Linux_fs/kernel/arch/arm/mach-omap1/board-fsample.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * linux/arch/arm/mach-omap1/board-fsample.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Modified from board-perseus2.c
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
8*4882a593Smuzhiyun  * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun #include <linux/gpio.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/mtd/mtd.h>
16*4882a593Smuzhiyun #include <linux/mtd/platnand.h>
17*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
18*4882a593Smuzhiyun #include <linux/input.h>
19*4882a593Smuzhiyun #include <linux/smc91x.h>
20*4882a593Smuzhiyun #include <linux/omapfb.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include <asm/mach-types.h>
23*4882a593Smuzhiyun #include <asm/mach/arch.h>
24*4882a593Smuzhiyun #include <asm/mach/map.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <mach/tc.h>
27*4882a593Smuzhiyun #include <mach/mux.h>
28*4882a593Smuzhiyun #include "flash.h"
29*4882a593Smuzhiyun #include <linux/platform_data/keypad-omap.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <mach/hardware.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include "iomap.h"
34*4882a593Smuzhiyun #include "common.h"
35*4882a593Smuzhiyun #include "fpga.h"
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* fsample is pretty close to p2-sample */
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define fsample_cpld_read(reg) __raw_readb(reg)
40*4882a593Smuzhiyun #define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define FSAMPLE_CPLD_BASE    0xE8100000
43*4882a593Smuzhiyun #define FSAMPLE_CPLD_SIZE    SZ_4K
44*4882a593Smuzhiyun #define FSAMPLE_CPLD_START   0x05080000
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define FSAMPLE_CPLD_REG_A   (FSAMPLE_CPLD_BASE + 0x00)
47*4882a593Smuzhiyun #define FSAMPLE_CPLD_SWITCH  (FSAMPLE_CPLD_BASE + 0x02)
48*4882a593Smuzhiyun #define FSAMPLE_CPLD_UART    (FSAMPLE_CPLD_BASE + 0x02)
49*4882a593Smuzhiyun #define FSAMPLE_CPLD_REG_B   (FSAMPLE_CPLD_BASE + 0x04)
50*4882a593Smuzhiyun #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
51*4882a593Smuzhiyun #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define FSAMPLE_CPLD_BIT_BT_RESET         0
54*4882a593Smuzhiyun #define FSAMPLE_CPLD_BIT_LCD_RESET        1
55*4882a593Smuzhiyun #define FSAMPLE_CPLD_BIT_CAM_PWDN         2
56*4882a593Smuzhiyun #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE   3
57*4882a593Smuzhiyun #define FSAMPLE_CPLD_BIT_SD_MMC_EN        4
58*4882a593Smuzhiyun #define FSAMPLE_CPLD_BIT_aGPS_PWREN       5
59*4882a593Smuzhiyun #define FSAMPLE_CPLD_BIT_BACKLIGHT        6
60*4882a593Smuzhiyun #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET    7
61*4882a593Smuzhiyun #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N    8
62*4882a593Smuzhiyun #define FSAMPLE_CPLD_BIT_OTG_RESET        9
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define fsample_cpld_set(bit) \
65*4882a593Smuzhiyun     fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define fsample_cpld_clear(bit) \
68*4882a593Smuzhiyun     fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun static const unsigned int fsample_keymap[] = {
71*4882a593Smuzhiyun 	KEY(0, 0, KEY_UP),
72*4882a593Smuzhiyun 	KEY(1, 0, KEY_RIGHT),
73*4882a593Smuzhiyun 	KEY(2, 0, KEY_LEFT),
74*4882a593Smuzhiyun 	KEY(3, 0, KEY_DOWN),
75*4882a593Smuzhiyun 	KEY(4, 0, KEY_ENTER),
76*4882a593Smuzhiyun 	KEY(0, 1, KEY_F10),
77*4882a593Smuzhiyun 	KEY(1, 1, KEY_SEND),
78*4882a593Smuzhiyun 	KEY(2, 1, KEY_END),
79*4882a593Smuzhiyun 	KEY(3, 1, KEY_VOLUMEDOWN),
80*4882a593Smuzhiyun 	KEY(4, 1, KEY_VOLUMEUP),
81*4882a593Smuzhiyun 	KEY(5, 1, KEY_RECORD),
82*4882a593Smuzhiyun 	KEY(0, 2, KEY_F9),
83*4882a593Smuzhiyun 	KEY(1, 2, KEY_3),
84*4882a593Smuzhiyun 	KEY(2, 2, KEY_6),
85*4882a593Smuzhiyun 	KEY(3, 2, KEY_9),
86*4882a593Smuzhiyun 	KEY(4, 2, KEY_KPDOT),
87*4882a593Smuzhiyun 	KEY(0, 3, KEY_BACK),
88*4882a593Smuzhiyun 	KEY(1, 3, KEY_2),
89*4882a593Smuzhiyun 	KEY(2, 3, KEY_5),
90*4882a593Smuzhiyun 	KEY(3, 3, KEY_8),
91*4882a593Smuzhiyun 	KEY(4, 3, KEY_0),
92*4882a593Smuzhiyun 	KEY(5, 3, KEY_KPSLASH),
93*4882a593Smuzhiyun 	KEY(0, 4, KEY_HOME),
94*4882a593Smuzhiyun 	KEY(1, 4, KEY_1),
95*4882a593Smuzhiyun 	KEY(2, 4, KEY_4),
96*4882a593Smuzhiyun 	KEY(3, 4, KEY_7),
97*4882a593Smuzhiyun 	KEY(4, 4, KEY_KPASTERISK),
98*4882a593Smuzhiyun 	KEY(5, 4, KEY_POWER),
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun static struct smc91x_platdata smc91x_info = {
102*4882a593Smuzhiyun 	.flags	= SMC91X_USE_16BIT | SMC91X_NOWAIT,
103*4882a593Smuzhiyun 	.leda	= RPC_LED_100_10,
104*4882a593Smuzhiyun 	.ledb	= RPC_LED_TX_RX,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun static struct resource smc91x_resources[] = {
108*4882a593Smuzhiyun 	[0] = {
109*4882a593Smuzhiyun 		.start	= H2P2_DBG_FPGA_ETHR_START,	/* Physical */
110*4882a593Smuzhiyun 		.end	= H2P2_DBG_FPGA_ETHR_START + 0xf,
111*4882a593Smuzhiyun 		.flags	= IORESOURCE_MEM,
112*4882a593Smuzhiyun 	},
113*4882a593Smuzhiyun 	[1] = {
114*4882a593Smuzhiyun 		.start	= INT_7XX_MPU_EXT_NIRQ,
115*4882a593Smuzhiyun 		.end	= 0,
116*4882a593Smuzhiyun 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
117*4882a593Smuzhiyun 	},
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
fsample_init_smc91x(void)120*4882a593Smuzhiyun static void __init fsample_init_smc91x(void)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	__raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
123*4882a593Smuzhiyun 	mdelay(50);
124*4882a593Smuzhiyun 	__raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
125*4882a593Smuzhiyun 		   H2P2_DBG_FPGA_LAN_RESET);
126*4882a593Smuzhiyun 	mdelay(50);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun static struct mtd_partition nor_partitions[] = {
130*4882a593Smuzhiyun 	/* bootloader (U-Boot, etc) in first sector */
131*4882a593Smuzhiyun 	{
132*4882a593Smuzhiyun 	      .name		= "bootloader",
133*4882a593Smuzhiyun 	      .offset		= 0,
134*4882a593Smuzhiyun 	      .size		= SZ_128K,
135*4882a593Smuzhiyun 	      .mask_flags	= MTD_WRITEABLE, /* force read-only */
136*4882a593Smuzhiyun 	},
137*4882a593Smuzhiyun 	/* bootloader params in the next sector */
138*4882a593Smuzhiyun 	{
139*4882a593Smuzhiyun 	      .name		= "params",
140*4882a593Smuzhiyun 	      .offset		= MTDPART_OFS_APPEND,
141*4882a593Smuzhiyun 	      .size		= SZ_128K,
142*4882a593Smuzhiyun 	      .mask_flags	= 0,
143*4882a593Smuzhiyun 	},
144*4882a593Smuzhiyun 	/* kernel */
145*4882a593Smuzhiyun 	{
146*4882a593Smuzhiyun 	      .name		= "kernel",
147*4882a593Smuzhiyun 	      .offset		= MTDPART_OFS_APPEND,
148*4882a593Smuzhiyun 	      .size		= SZ_2M,
149*4882a593Smuzhiyun 	      .mask_flags	= 0
150*4882a593Smuzhiyun 	},
151*4882a593Smuzhiyun 	/* rest of flash is a file system */
152*4882a593Smuzhiyun 	{
153*4882a593Smuzhiyun 	      .name		= "rootfs",
154*4882a593Smuzhiyun 	      .offset		= MTDPART_OFS_APPEND,
155*4882a593Smuzhiyun 	      .size		= MTDPART_SIZ_FULL,
156*4882a593Smuzhiyun 	      .mask_flags	= 0
157*4882a593Smuzhiyun 	},
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun static struct physmap_flash_data nor_data = {
161*4882a593Smuzhiyun 	.width		= 2,
162*4882a593Smuzhiyun 	.set_vpp	= omap1_set_vpp,
163*4882a593Smuzhiyun 	.parts		= nor_partitions,
164*4882a593Smuzhiyun 	.nr_parts	= ARRAY_SIZE(nor_partitions),
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun static struct resource nor_resource = {
168*4882a593Smuzhiyun 	.start		= OMAP_CS0_PHYS,
169*4882a593Smuzhiyun 	.end		= OMAP_CS0_PHYS + SZ_32M - 1,
170*4882a593Smuzhiyun 	.flags		= IORESOURCE_MEM,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun static struct platform_device nor_device = {
174*4882a593Smuzhiyun 	.name		= "physmap-flash",
175*4882a593Smuzhiyun 	.id		= 0,
176*4882a593Smuzhiyun 	.dev		= {
177*4882a593Smuzhiyun 		.platform_data	= &nor_data,
178*4882a593Smuzhiyun 	},
179*4882a593Smuzhiyun 	.num_resources	= 1,
180*4882a593Smuzhiyun 	.resource	= &nor_resource,
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun #define FSAMPLE_NAND_RB_GPIO_PIN	62
184*4882a593Smuzhiyun 
nand_dev_ready(struct nand_chip * chip)185*4882a593Smuzhiyun static int nand_dev_ready(struct nand_chip *chip)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun 	return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static struct platform_nand_data nand_data = {
191*4882a593Smuzhiyun 	.chip	= {
192*4882a593Smuzhiyun 		.nr_chips		= 1,
193*4882a593Smuzhiyun 		.chip_offset		= 0,
194*4882a593Smuzhiyun 		.options		= NAND_SAMSUNG_LP_OPTIONS,
195*4882a593Smuzhiyun 	},
196*4882a593Smuzhiyun 	.ctrl	= {
197*4882a593Smuzhiyun 		.cmd_ctrl	= omap1_nand_cmd_ctl,
198*4882a593Smuzhiyun 		.dev_ready	= nand_dev_ready,
199*4882a593Smuzhiyun 	},
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static struct resource nand_resource = {
203*4882a593Smuzhiyun 	.start		= OMAP_CS3_PHYS,
204*4882a593Smuzhiyun 	.end		= OMAP_CS3_PHYS + SZ_4K - 1,
205*4882a593Smuzhiyun 	.flags		= IORESOURCE_MEM,
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static struct platform_device nand_device = {
209*4882a593Smuzhiyun 	.name		= "gen_nand",
210*4882a593Smuzhiyun 	.id		= 0,
211*4882a593Smuzhiyun 	.dev		= {
212*4882a593Smuzhiyun 		.platform_data	= &nand_data,
213*4882a593Smuzhiyun 	},
214*4882a593Smuzhiyun 	.num_resources	= 1,
215*4882a593Smuzhiyun 	.resource	= &nand_resource,
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun static struct platform_device smc91x_device = {
219*4882a593Smuzhiyun 	.name		= "smc91x",
220*4882a593Smuzhiyun 	.id		= 0,
221*4882a593Smuzhiyun 	.dev	= {
222*4882a593Smuzhiyun 		.platform_data	= &smc91x_info,
223*4882a593Smuzhiyun 	},
224*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(smc91x_resources),
225*4882a593Smuzhiyun 	.resource	= smc91x_resources,
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun static struct resource kp_resources[] = {
229*4882a593Smuzhiyun 	[0] = {
230*4882a593Smuzhiyun 		.start	= INT_7XX_MPUIO_KEYPAD,
231*4882a593Smuzhiyun 		.end	= INT_7XX_MPUIO_KEYPAD,
232*4882a593Smuzhiyun 		.flags	= IORESOURCE_IRQ,
233*4882a593Smuzhiyun 	},
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun static const struct matrix_keymap_data fsample_keymap_data = {
237*4882a593Smuzhiyun 	.keymap		= fsample_keymap,
238*4882a593Smuzhiyun 	.keymap_size	= ARRAY_SIZE(fsample_keymap),
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun static struct omap_kp_platform_data kp_data = {
242*4882a593Smuzhiyun 	.rows		= 8,
243*4882a593Smuzhiyun 	.cols		= 8,
244*4882a593Smuzhiyun 	.keymap_data	= &fsample_keymap_data,
245*4882a593Smuzhiyun 	.delay		= 4,
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun static struct platform_device kp_device = {
249*4882a593Smuzhiyun 	.name		= "omap-keypad",
250*4882a593Smuzhiyun 	.id		= -1,
251*4882a593Smuzhiyun 	.dev		= {
252*4882a593Smuzhiyun 		.platform_data = &kp_data,
253*4882a593Smuzhiyun 	},
254*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(kp_resources),
255*4882a593Smuzhiyun 	.resource	= kp_resources,
256*4882a593Smuzhiyun };
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun static struct platform_device *devices[] __initdata = {
259*4882a593Smuzhiyun 	&nor_device,
260*4882a593Smuzhiyun 	&nand_device,
261*4882a593Smuzhiyun 	&smc91x_device,
262*4882a593Smuzhiyun 	&kp_device,
263*4882a593Smuzhiyun };
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun static const struct omap_lcd_config fsample_lcd_config = {
266*4882a593Smuzhiyun 	.ctrl_name	= "internal",
267*4882a593Smuzhiyun };
268*4882a593Smuzhiyun 
omap_fsample_init(void)269*4882a593Smuzhiyun static void __init omap_fsample_init(void)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun 	/* Early, board-dependent init */
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	/*
274*4882a593Smuzhiyun 	 * Hold GSM Reset until needed
275*4882a593Smuzhiyun 	 */
276*4882a593Smuzhiyun 	omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	/*
279*4882a593Smuzhiyun 	 * UARTs -> done automagically by 8250 driver
280*4882a593Smuzhiyun 	 */
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	/*
283*4882a593Smuzhiyun 	 * CSx timings, GPIO Mux ... setup
284*4882a593Smuzhiyun 	 */
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	/* Flash: CS0 timings setup */
287*4882a593Smuzhiyun 	omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
288*4882a593Smuzhiyun 	omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	/*
291*4882a593Smuzhiyun 	 * Ethernet support through the debug board
292*4882a593Smuzhiyun 	 * CS1 timings setup
293*4882a593Smuzhiyun 	 */
294*4882a593Smuzhiyun 	omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
295*4882a593Smuzhiyun 	omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	/*
298*4882a593Smuzhiyun 	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
299*4882a593Smuzhiyun 	 * It is used as the Ethernet controller interrupt
300*4882a593Smuzhiyun 	 */
301*4882a593Smuzhiyun 	omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF,
302*4882a593Smuzhiyun 			OMAP7XX_IO_CONF_9);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	fsample_init_smc91x();
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	BUG_ON(gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0);
307*4882a593Smuzhiyun 	gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
310*4882a593Smuzhiyun 	omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	/* Mux pins for keypad */
313*4882a593Smuzhiyun 	omap_cfg_reg(E2_7XX_KBR0);
314*4882a593Smuzhiyun 	omap_cfg_reg(J7_7XX_KBR1);
315*4882a593Smuzhiyun 	omap_cfg_reg(E1_7XX_KBR2);
316*4882a593Smuzhiyun 	omap_cfg_reg(F3_7XX_KBR3);
317*4882a593Smuzhiyun 	omap_cfg_reg(D2_7XX_KBR4);
318*4882a593Smuzhiyun 	omap_cfg_reg(C2_7XX_KBC0);
319*4882a593Smuzhiyun 	omap_cfg_reg(D3_7XX_KBC1);
320*4882a593Smuzhiyun 	omap_cfg_reg(E4_7XX_KBC2);
321*4882a593Smuzhiyun 	omap_cfg_reg(F4_7XX_KBC3);
322*4882a593Smuzhiyun 	omap_cfg_reg(E3_7XX_KBC4);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	platform_add_devices(devices, ARRAY_SIZE(devices));
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	omap_serial_init();
327*4882a593Smuzhiyun 	omap_register_i2c_bus(1, 100, NULL, 0);
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	omapfb_set_lcd_config(&fsample_lcd_config);
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun /* Only FPGA needs to be mapped here. All others are done with ioremap */
333*4882a593Smuzhiyun static struct map_desc omap_fsample_io_desc[] __initdata = {
334*4882a593Smuzhiyun 	{
335*4882a593Smuzhiyun 		.virtual	= H2P2_DBG_FPGA_BASE,
336*4882a593Smuzhiyun 		.pfn		= __phys_to_pfn(H2P2_DBG_FPGA_START),
337*4882a593Smuzhiyun 		.length		= H2P2_DBG_FPGA_SIZE,
338*4882a593Smuzhiyun 		.type		= MT_DEVICE
339*4882a593Smuzhiyun 	},
340*4882a593Smuzhiyun 	{
341*4882a593Smuzhiyun 		.virtual	= FSAMPLE_CPLD_BASE,
342*4882a593Smuzhiyun 		.pfn		= __phys_to_pfn(FSAMPLE_CPLD_START),
343*4882a593Smuzhiyun 		.length		= FSAMPLE_CPLD_SIZE,
344*4882a593Smuzhiyun 		.type		= MT_DEVICE
345*4882a593Smuzhiyun 	}
346*4882a593Smuzhiyun };
347*4882a593Smuzhiyun 
omap_fsample_map_io(void)348*4882a593Smuzhiyun static void __init omap_fsample_map_io(void)
349*4882a593Smuzhiyun {
350*4882a593Smuzhiyun 	omap15xx_map_io();
351*4882a593Smuzhiyun 	iotable_init(omap_fsample_io_desc,
352*4882a593Smuzhiyun 		     ARRAY_SIZE(omap_fsample_io_desc));
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
356*4882a593Smuzhiyun /* Maintainer: Brian Swetland <swetland@google.com> */
357*4882a593Smuzhiyun 	.atag_offset	= 0x100,
358*4882a593Smuzhiyun 	.map_io		= omap_fsample_map_io,
359*4882a593Smuzhiyun 	.init_early	= omap1_init_early,
360*4882a593Smuzhiyun 	.init_irq	= omap1_init_irq,
361*4882a593Smuzhiyun 	.handle_irq	= omap1_handle_irq,
362*4882a593Smuzhiyun 	.init_machine	= omap_fsample_init,
363*4882a593Smuzhiyun 	.init_late	= omap1_init_late,
364*4882a593Smuzhiyun 	.init_time	= omap1_timer_init,
365*4882a593Smuzhiyun 	.restart	= omap1_restart,
366*4882a593Smuzhiyun MACHINE_END
367