1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2018 Nuvoton Technology corporation.
3*4882a593Smuzhiyun // Copyright 2018 Google, Inc.
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/smp.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun #include <asm/cacheflush.h>
16*4882a593Smuzhiyun #include <asm/smp.h>
17*4882a593Smuzhiyun #include <asm/smp_plat.h>
18*4882a593Smuzhiyun #include <asm/smp_scu.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define NPCM7XX_SCRPAD_REG 0x13c
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun extern void npcm7xx_secondary_startup(void);
23*4882a593Smuzhiyun
npcm7xx_smp_boot_secondary(unsigned int cpu,struct task_struct * idle)24*4882a593Smuzhiyun static int npcm7xx_smp_boot_secondary(unsigned int cpu,
25*4882a593Smuzhiyun struct task_struct *idle)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct device_node *gcr_np;
28*4882a593Smuzhiyun void __iomem *gcr_base;
29*4882a593Smuzhiyun int ret = 0;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
32*4882a593Smuzhiyun if (!gcr_np) {
33*4882a593Smuzhiyun pr_err("no gcr device node\n");
34*4882a593Smuzhiyun ret = -ENODEV;
35*4882a593Smuzhiyun goto out;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun gcr_base = of_iomap(gcr_np, 0);
38*4882a593Smuzhiyun if (!gcr_base) {
39*4882a593Smuzhiyun pr_err("could not iomap gcr");
40*4882a593Smuzhiyun ret = -ENOMEM;
41*4882a593Smuzhiyun goto out;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* give boot ROM kernel start address. */
45*4882a593Smuzhiyun iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
46*4882a593Smuzhiyun NPCM7XX_SCRPAD_REG);
47*4882a593Smuzhiyun /* make sure the previous write is seen by all observers. */
48*4882a593Smuzhiyun dsb_sev();
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun iounmap(gcr_base);
51*4882a593Smuzhiyun out:
52*4882a593Smuzhiyun return ret;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
npcm7xx_smp_prepare_cpus(unsigned int max_cpus)55*4882a593Smuzhiyun static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct device_node *scu_np;
58*4882a593Smuzhiyun void __iomem *scu_base;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
61*4882a593Smuzhiyun if (!scu_np) {
62*4882a593Smuzhiyun pr_err("no scu device node\n");
63*4882a593Smuzhiyun return;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun scu_base = of_iomap(scu_np, 0);
66*4882a593Smuzhiyun if (!scu_base) {
67*4882a593Smuzhiyun pr_err("could not iomap scu");
68*4882a593Smuzhiyun return;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun scu_enable(scu_base);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun iounmap(scu_base);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static struct smp_operations npcm7xx_smp_ops __initdata = {
77*4882a593Smuzhiyun .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
78*4882a593Smuzhiyun .smp_boot_secondary = npcm7xx_smp_boot_secondary,
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm750-smp", &npcm7xx_smp_ops);
82