1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2014 Marvell 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 5*4882a593Smuzhiyun * Gregory Clement <gregory.clement@free-electrons.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 8*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 9*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include <linux/linkage.h> 13*4882a593Smuzhiyun#include <asm/assembler.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunENTRY(armada_38x_scu_power_up) 17*4882a593Smuzhiyun mrc p15, 4, r1, c15, c0 @ get SCU base address 18*4882a593Smuzhiyun orr r1, r1, #0x8 @ SCU CPU Power Status Register 19*4882a593Smuzhiyun mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID 20*4882a593Smuzhiyun and r0, r0, #15 21*4882a593Smuzhiyun add r1, r1, r0 22*4882a593Smuzhiyun mov r0, #0x0 23*4882a593Smuzhiyun strb r0, [r1] @ switch SCU power state to Normal mode 24*4882a593Smuzhiyun ret lr 25*4882a593SmuzhiyunENDPROC(armada_38x_scu_power_up) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun/* 28*4882a593Smuzhiyun * This is the entry point through which CPUs exiting cpuidle deep 29*4882a593Smuzhiyun * idle state are going. 30*4882a593Smuzhiyun */ 31*4882a593SmuzhiyunENTRY(armada_370_xp_cpu_resume) 32*4882a593SmuzhiyunARM_BE8(setend be ) @ go BE8 if entered LE 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * Disable the MMU that might have been enabled in BootROM if 35*4882a593Smuzhiyun * this code is used in the resume path of a suspend/resume 36*4882a593Smuzhiyun * cycle. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun mrc p15, 0, r1, c1, c0, 0 39*4882a593Smuzhiyun bic r1, #1 40*4882a593Smuzhiyun mcr p15, 0, r1, c1, c0, 0 41*4882a593Smuzhiyun bl ll_add_cpu_to_smp_group 42*4882a593Smuzhiyun bl ll_enable_coherency 43*4882a593Smuzhiyun b cpu_resume 44*4882a593SmuzhiyunENDPROC(armada_370_xp_cpu_resume) 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunENTRY(armada_38x_cpu_resume) 47*4882a593Smuzhiyun /* do we need it for Armada 38x*/ 48*4882a593SmuzhiyunARM_BE8(setend be ) @ go BE8 if entered LE 49*4882a593Smuzhiyun bl v7_invalidate_l1 50*4882a593Smuzhiyun bl armada_38x_scu_power_up 51*4882a593Smuzhiyun b cpu_resume 52*4882a593SmuzhiyunENDPROC(armada_38x_cpu_resume) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun.global mvebu_boot_wa_start 55*4882a593Smuzhiyun.global mvebu_boot_wa_end 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun/* The following code will be executed from SRAM */ 58*4882a593SmuzhiyunENTRY(mvebu_boot_wa_start) 59*4882a593SmuzhiyunARM_BE8(setend be) 60*4882a593Smuzhiyun adr r0, 1f 61*4882a593Smuzhiyun ldr r0, [r0] @ load the address of the 62*4882a593Smuzhiyun @ resume register 63*4882a593Smuzhiyun ldr r0, [r0] @ load the value in the 64*4882a593Smuzhiyun @ resume register 65*4882a593SmuzhiyunARM_BE8(rev r0, r0) @ the value is stored LE 66*4882a593Smuzhiyun mov pc, r0 @ jump to this value 67*4882a593Smuzhiyun/* 68*4882a593Smuzhiyun * the last word of this piece of code will be filled by the physical 69*4882a593Smuzhiyun * address of the boot address register just after being copied in SRAM 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun1: 72*4882a593Smuzhiyun .long . 73*4882a593Smuzhiyunmvebu_boot_wa_end: 74*4882a593SmuzhiyunENDPROC(mvebu_boot_wa_end) 75