1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Power Management driver for Marvell Kirkwood SoCs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com> 6*4882a593Smuzhiyun * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/kernel.h> 10*4882a593Smuzhiyun #include <linux/suspend.h> 11*4882a593Smuzhiyun #include <linux/io.h> 12*4882a593Smuzhiyun #include "kirkwood.h" 13*4882a593Smuzhiyun #include "kirkwood-pm.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun static void __iomem *ddr_operation_base; 16*4882a593Smuzhiyun static void __iomem *memory_pm_ctrl; 17*4882a593Smuzhiyun kirkwood_low_power(void)18*4882a593Smuzhiyunstatic void kirkwood_low_power(void) 19*4882a593Smuzhiyun { 20*4882a593Smuzhiyun u32 mem_pm_ctrl; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun mem_pm_ctrl = readl(memory_pm_ctrl); 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Set peripherals to low-power mode */ 25*4882a593Smuzhiyun writel_relaxed(~0, memory_pm_ctrl); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Set DDR in self-refresh */ 28*4882a593Smuzhiyun writel_relaxed(0x7, ddr_operation_base); 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * Set CPU in wait-for-interrupt state. 32*4882a593Smuzhiyun * This disables the CPU core clocks, 33*4882a593Smuzhiyun * the array clocks, and also the L2 controller. 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun cpu_do_idle(); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun writel_relaxed(mem_pm_ctrl, memory_pm_ctrl); 38*4882a593Smuzhiyun } 39*4882a593Smuzhiyun kirkwood_suspend_enter(suspend_state_t state)40*4882a593Smuzhiyunstatic int kirkwood_suspend_enter(suspend_state_t state) 41*4882a593Smuzhiyun { 42*4882a593Smuzhiyun switch (state) { 43*4882a593Smuzhiyun case PM_SUSPEND_STANDBY: 44*4882a593Smuzhiyun kirkwood_low_power(); 45*4882a593Smuzhiyun break; 46*4882a593Smuzhiyun default: 47*4882a593Smuzhiyun return -EINVAL; 48*4882a593Smuzhiyun } 49*4882a593Smuzhiyun return 0; 50*4882a593Smuzhiyun } 51*4882a593Smuzhiyun kirkwood_pm_valid_standby(suspend_state_t state)52*4882a593Smuzhiyunstatic int kirkwood_pm_valid_standby(suspend_state_t state) 53*4882a593Smuzhiyun { 54*4882a593Smuzhiyun return state == PM_SUSPEND_STANDBY; 55*4882a593Smuzhiyun } 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun static const struct platform_suspend_ops kirkwood_suspend_ops = { 58*4882a593Smuzhiyun .enter = kirkwood_suspend_enter, 59*4882a593Smuzhiyun .valid = kirkwood_pm_valid_standby, 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun kirkwood_pm_init(void)62*4882a593Smuzhiyunvoid __init kirkwood_pm_init(void) 63*4882a593Smuzhiyun { 64*4882a593Smuzhiyun ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4); 65*4882a593Smuzhiyun memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun suspend_set_ops(&kirkwood_suspend_ops); 68*4882a593Smuzhiyun } 69